/drivers/clk/st/ |
D | clkgen-pll.c | 263 pr_debug("%s:%s enabled\n", __clk_get_name(hw->clk), __func__); in __clkgen_pll_enable() 298 pr_debug("%s:%s disabled\n", __clk_get_name(hw->clk), __func__); in __clkgen_pll_disable() 407 __clk_get_name(hw->clk), rate); in round_rate_stm_pll3200c32() 412 __func__, __clk_get_name(hw->clk), in round_rate_stm_pll3200c32() 434 __func__, __clk_get_name(hw->clk), in set_rate_stm_pll3200c32() 547 pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate); in recalc_stm_pll4600c28() 561 __clk_get_name(hw->clk), rate); in round_rate_stm_pll4600c28() 566 __func__, __clk_get_name(hw->clk), in round_rate_stm_pll4600c28() 588 __clk_get_name(hw->clk), rate); in set_rate_stm_pll4600c28() 593 __func__, __clk_get_name(hw->clk), in set_rate_stm_pll4600c28() [all …]
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D | clkgen-mux.c | 92 __clk_get_name(clk), in st_of_clkgen_mux_setup() 93 __clk_get_name(clk_get_parent(clk)), in st_of_clkgen_mux_setup()
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D | clkgen-fsyn.c | 974 __clk_get_name(clk), in st_of_create_quadfs_fsynths() 975 __clk_get_name(clk_get_parent(clk)), in st_of_create_quadfs_fsynths() 1028 __clk_get_name(clk), in st_of_quadfs_setup() 1029 __clk_get_name(clk_get_parent(clk)), in st_of_quadfs_setup()
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/drivers/clk/renesas/ |
D | rcar-gen4-cpg.c | 239 return cpg_z_clk_register(core->name, __clk_get_name(parent), in rcar_gen4_cpg_clk_register() 248 __clk_get_name(parent), notifiers); in rcar_gen4_cpg_clk_register() 252 __clk_get_name(parent)); in rcar_gen4_cpg_clk_register() 279 __clk_get_name(parent), 0, in rcar_gen4_cpg_clk_register() 286 __clk_get_name(parent), notifiers); in rcar_gen4_cpg_clk_register() 290 __clk_get_name(parent)); in rcar_gen4_cpg_clk_register() 297 __clk_get_name(parent), 0, mult, div); in rcar_gen4_cpg_clk_register()
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D | rcar-gen3-cpg.c | 349 return cpg_pll_clk_register(core->name, __clk_get_name(parent), in rcar_gen3_cpg_clk_register() 363 return cpg_pll_clk_register(core->name, __clk_get_name(parent), in rcar_gen3_cpg_clk_register() 384 __clk_get_name(parent), notifiers); in rcar_gen3_cpg_clk_register() 388 __clk_get_name(parent)); in rcar_gen3_cpg_clk_register() 438 return cpg_z_clk_register(core->name, __clk_get_name(parent), in rcar_gen3_cpg_clk_register() 465 __clk_get_name(parent), 0, in rcar_gen3_cpg_clk_register() 500 __clk_get_name(parent), notifiers); in rcar_gen3_cpg_clk_register() 504 __clk_get_name(parent)); in rcar_gen3_cpg_clk_register() 511 __clk_get_name(parent), 0, mult, div); in rcar_gen3_cpg_clk_register()
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D | rzg2l-cpg.c | 137 parent_name = __clk_get_name(parent); in rzg2l_cpg_div_clk_register() 412 parent_name = __clk_get_name(parent); in rzg2l_cpg_dsi_div_clk_register() 659 parent_name = __clk_get_name(parent); in rzg2l_cpg_sipll5_register() 740 parent_name = __clk_get_name(parent); in rzg2l_cpg_pll_clk_register() 831 parent_name = __clk_get_name(parent); in rzg2l_cpg_register_core_clk() 1082 parent_name = __clk_get_name(parent); in rzg2l_cpg_register_mod_clk()
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/drivers/clk/samsung/ |
D | clk-s5pv210-audss.c | 109 mout_audss_p[0] = __clk_get_name(pll_ref); in s5pv210_audss_clk_probe() 112 mout_audss_p[1] = __clk_get_name(pll_in); in s5pv210_audss_clk_probe() 120 mout_i2s_p[1] = __clk_get_name(cdclk); in s5pv210_audss_clk_probe() 123 mout_i2s_p[2] = __clk_get_name(sclk_audio); in s5pv210_audss_clk_probe() 140 hclk_p = __clk_get_name(hclk); in s5pv210_audss_clk_probe()
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D | clk-exynos-audss.c | 158 mout_audss_p[0] = __clk_get_name(pll_ref); in exynos_audss_clk_probe() 160 mout_audss_p[1] = __clk_get_name(pll_in); in exynos_audss_clk_probe() 192 mout_i2s_p[1] = __clk_get_name(cdclk); in exynos_audss_clk_probe() 194 mout_i2s_p[2] = __clk_get_name(sclk_audio); in exynos_audss_clk_probe() 230 sclk_pcm_p = __clk_get_name(sclk_pcm_in); in exynos_audss_clk_probe()
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/drivers/clk/ |
D | clk-conf.c | 71 __clk_get_name(clk), __clk_get_name(pclk), rc); in __set_clk_parents() 118 __clk_get_name(clk), rate, rc, in __set_clk_rates()
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/drivers/clk/tegra/ |
D | clk.c | 288 __func__, __clk_get_name(parent), in tegra_init_from_table() 289 __clk_get_name(clk)); in tegra_init_from_table() 298 __clk_get_name(clk)); in tegra_init_from_table() 305 __clk_get_name(clk)); in tegra_init_from_table() 368 clk_register_clkdev(clks[i], __clk_get_name(clks[i]), in tegra_register_devclks()
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D | clk-tegra124-emc.c | 222 timing->parent_rate, __clk_get_name(timing->parent)); in emc_set_timing() 227 __clk_get_name(timing->parent), in emc_set_timing() 238 __clk_get_name(timing->parent), timing->parent_rate, in emc_set_timing() 417 __clk_get_name(timing->parent)); in load_one_timing_from_dt() 420 node, __clk_get_name(timing->parent)); in load_one_timing_from_dt()
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/drivers/clk/rockchip/ |
D | clk-pll.c | 255 __func__, __clk_get_name(hw->clk), drate, prate); in rockchip_rk3036_pll_set_rate() 261 drate, __clk_get_name(hw->clk)); in rockchip_rk3036_pll_set_rate() 315 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), in rockchip_rk3036_pll_init() 332 __func__, __clk_get_name(hw->clk)); in rockchip_rk3036_pll_init() 337 __func__, __clk_get_name(hw->clk)); in rockchip_rk3036_pll_init() 739 __func__, __clk_get_name(hw->clk), drate, prate); in rockchip_rk3399_pll_set_rate() 745 drate, __clk_get_name(hw->clk)); in rockchip_rk3399_pll_set_rate() 799 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), in rockchip_rk3399_pll_init() 816 __func__, __clk_get_name(hw->clk)); in rockchip_rk3399_pll_init() 821 __func__, __clk_get_name(hw->clk)); in rockchip_rk3399_pll_init()
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/drivers/clk/ti/ |
D | clockdomain.c | 107 clk_name = __clk_get_name(hw->clk); in omap2_init_clk_clkdm() 142 __clk_get_name(clk)); in of_ti_clockdomain_setup()
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D | adpll.c | 248 parent_name = __clk_get_name(parent_clock); in ti_adpll_init_divider() 276 parents[0] = __clk_get_name(clk0); in ti_adpll_init_mux() 277 parents[1] = __clk_get_name(clk1); in ti_adpll_init_mux() 306 parent_name = __clk_get_name(parent_clock); in ti_adpll_init_gate() 335 parent_name = __clk_get_name(parent_clock); in ti_adpll_init_fixed_factor() 604 parent_names[0] = __clk_get_name(clk0); in ti_adpll_init_clkout() 605 parent_names[1] = __clk_get_name(clk1); in ti_adpll_init_clkout()
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/drivers/clk/sunxi/ |
D | clk-a10-pll2.c | 94 parent = __clk_get_name(prediv_clk); in sun4i_pll2_setup() 106 parent = __clk_get_name(base_clk); in sun4i_pll2_setup()
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/drivers/gpu/drm/sun4i/ |
D | sun8i_hdmi_phy_clk.c | 150 parents[0] = __clk_get_name(phy->clk_pll0); in sun8i_phy_clk_create() 155 parents[1] = __clk_get_name(phy->clk_pll1); in sun8i_phy_clk_create()
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D | sun4i_hdmi_tmds_clk.c | 209 parents[0] = __clk_get_name(hdmi->pll0_clk); in sun4i_tmds_create() 213 parents[1] = __clk_get_name(hdmi->pll1_clk); in sun4i_tmds_create()
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D | sun4i_hdmi_ddc_clk.c | 114 parent_name = __clk_get_name(parent); in sun4i_ddc_create()
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/drivers/cpufreq/ |
D | loongson1-cpufreq.c | 166 __clk_get_name(cpufreq->clk)); in ls1x_cpufreq_probe() 174 __clk_get_name(cpufreq->mux_clk)); in ls1x_cpufreq_probe()
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/drivers/clk/microchip/ |
D | clk-pic32mzda.c | 223 clk_register_clkdev(clks[i], NULL, __clk_get_name(clks[i])); in pic32mzda_clk_probe() 239 __clk_get_name(clk)); in pic32mzda_clk_probe()
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/drivers/mfd/ |
D | intel-lpss.c | 297 tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0, in intel_lpss_register_clock_divider() 303 tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp), in intel_lpss_register_clock_divider() 312 tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), in intel_lpss_register_clock_divider()
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/drivers/pwm/ |
D | pwm-meson.c | 131 __clk_get_name(channel->clk_parent), in meson_pwm_request() 132 __clk_get_name(channel->clk), err); in meson_pwm_request() 140 __clk_get_name(channel->clk), err); in meson_pwm_request()
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/drivers/clk/bcm/ |
D | clk-bcm2835-aux.c | 27 parent = __clk_get_name(parent_clk); in bcm2835_aux_clk_probe()
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/drivers/net/mdio/ |
D | mdio-mux-meson-g12a.c | 249 parent_names[i] = __clk_get_name(clk); in g12a_ephy_glue_clk_register() 291 parent_names[0] = __clk_get_name(clk); in g12a_ephy_glue_clk_register()
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/drivers/clk/mvebu/ |
D | armada-37xx-tbg.c | 105 parent_name = __clk_get_name(parent); in armada_3700_tbg_clock_probe()
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