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Searched refs:cfgcr0 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.h208 u32 cfgcr0; member
Dintel_dpll_mgr.c2750 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * in icl_ddi_combo_pll_get_freq()
2753 dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> in icl_ddi_combo_pll_get_freq()
2776 pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) | in icl_calc_dpll_state()
3580 hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3583 hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3586 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3591 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3601 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3606 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3665 intel_de_write(dev_priv, cfgcr0_reg, hw_state->cfgcr0); in icl_dpll_write()
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Dintel_display_debugfs.c957 seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); in i915_shared_dplls_info()
Dintel_display.c5846 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); in intel_pipe_config_compare()