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Searched refs:clk_hw_get_rate (Results 1 – 25 of 67) sorted by relevance

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/drivers/clk/sunxi-ng/
Dccu_phase.c35 parent_rate = clk_hw_get_rate(parent); in ccu_phase_get_phase()
45 grandparent_rate = clk_hw_get_rate(grandparent); in ccu_phase_get_phase()
71 parent_rate = clk_hw_get_rate(parent); in ccu_phase_set_phase()
81 grandparent_rate = clk_hw_get_rate(grandparent); in ccu_phase_set_phase()
Dccu_mux.c97 best_parent_rate = clk_hw_get_rate(best_parent); in ccu_mux_helper_determine_rate()
124 clk_hw_get_rate(parent)); in ccu_mux_helper_determine_rate()
/drivers/clk/ti/
Dclkt_dpll.c76 fint = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)) / n; in _dpll_test_fint()
254 return clk_hw_get_rate(dd->clk_bypass); in omap2_get_dpll_rate()
262 dpll_clk = (u64)clk_hw_get_rate(dd->clk_ref) * dpll_mult; in omap2_get_dpll_rate()
305 ref_rate = clk_hw_get_rate(dd->clk_ref); in omap2_dpll_round_rate()
Ddpll3xxx.c98 fint = clk_hw_get_rate(clk->dpll_data->clk_ref) / n; in _omap3_dpll_compute_freqsel()
251 clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)); in _lookup_dco()
277 clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)); in _lookup_sddiv()
318 ref_rate = clk_hw_get_rate(dd->clk_ref); in omap3_noncore_dpll_ssc_program()
546 if (clk_hw_get_rate(hw) == clk_hw_get_rate(dd->clk_bypass)) { in omap3_noncore_dpll_enable()
598 if (clk_hw_get_rate(dd->clk_bypass) == req->rate && in omap3_noncore_dpll_determine_rate()
Ddpll44xx.c94 fint = clk_hw_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1); in omap4_dpll_lpmode_recalc()
214 if (clk_hw_get_rate(dd->clk_bypass) == req->rate && in omap4_dpll_regm4xen_determine_rate()
/drivers/clk/tegra/
Dclk-tegra210-emc.c79 parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); in tegra210_clk_emc_recalc_rate()
97 return clk_hw_get_rate(hw); in tegra210_clk_emc_round_rate()
151 if (config->parent_rate != clk_hw_get_rate(old)) { in tegra210_clk_emc_set_rate()
342 config->parent_rate = clk_hw_get_rate(parent); in tegra210_clk_emc_attach()
Dclk-divider.c120 unsigned long parent_rate = clk_hw_get_rate(parent); in clk_divider_restore_context()
121 unsigned long rate = clk_hw_get_rate(hw); in clk_divider_restore_context()
Dclk-tegra124-emc.c103 parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); in emc_recalc_rate()
159 req->rate = clk_hw_get_rate(hw); in emc_determine_rate()
331 if (clk_hw_get_rate(hw) == rate) in emc_set_rate()
Dclk-sdmmc-mux.c209 unsigned long parent_rate = clk_hw_get_rate(parent); in clk_sdmmc_mux_restore_context()
210 unsigned long rate = clk_hw_get_rate(hw); in clk_sdmmc_mux_restore_context()
Dclk-device.c102 rate = clk_hw_get_rate(clk_dev->hw); in tegra_clock_sync_pd_state()
/drivers/clk/at91/
Dclk-utmi.c55 parent_rate = clk_hw_get_rate(hw_parent); in clk_utmi_prepare()
194 parent_rate = clk_hw_get_rate(hw_parent); in clk_utmi_sama7g5_prepare()
228 parent_rate = clk_hw_get_rate(hw_parent); in clk_utmi_sama7g5_is_prepared()
Dclk-programmable.c67 parent_rate = clk_hw_get_rate(parent); in clk_programmable_determine_rate()
187 prog->pms.parent_rate = clk_hw_get_rate(parent_hw); in clk_programmable_save_context()
/drivers/clk/mmp/
Dclk-mix.c121 parent_rate = clk_hw_get_rate(parent); in _filter_clk_table()
226 parent_rate = clk_hw_get_rate(parent); in mmp_clk_mix_determine_rate()
241 parent_rate = clk_hw_get_rate(parent); in mmp_clk_mix_determine_rate()
392 parent_rate = clk_hw_get_rate(parent); in mmp_clk_set_rate()
407 parent_rate = clk_hw_get_rate(parent); in mmp_clk_set_rate()
Dclk-gate.c43 rate = clk_hw_get_rate(hw); in mmp_clk_gate_enable()
/drivers/clk/qcom/
Dclk-regmap-mux-div.c98 unsigned long parent_rate = clk_hw_get_rate(parent); in mux_div_determine_rate()
135 unsigned long parent_rate = clk_hw_get_rate(parent); in __mux_div_set_rate_and_parent()
214 unsigned long parent_rate = clk_hw_get_rate(p); in mux_div_recalc_rate()
Dclk-rcg2.c254 rate = clk_hw_get_rate(p); in _freq_tbl_determine_rate()
600 req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw); in clk_edp_pixel_determine_rate()
881 if (req->rate == clk_hw_get_rate(xo)) { in clk_gfx3d_determine_rate()
892 p0_rate = clk_hw_get_rate(p0); in clk_gfx3d_determine_rate()
902 if (clk_hw_get_rate(p2) == parent_req.rate) in clk_gfx3d_determine_rate()
1176 prate = clk_hw_get_rate(p); in clk_rcg2_dfs_populate_freq()
/drivers/clk/rockchip/
Dclk-mmc-phase.c49 unsigned long rate = clk_hw_get_rate(hw); in rockchip_mmc_get_phase()
78 unsigned long rate = clk_hw_get_rate(hw); in rockchip_mmc_set_phase()
/drivers/clk/samsung/
Dclk-exynos4.c1267 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) { in exynos4_clk_init()
1274 if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24000000) in exynos4_clk_init()
1281 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) { in exynos4_clk_init()
1352 clk_hw_get_rate(hws[CLK_SCLK_APLL]), in exynos4_clk_init()
1353 clk_hw_get_rate(hws[CLK_SCLK_MPLL]), in exynos4_clk_init()
1354 clk_hw_get_rate(hws[CLK_SCLK_EPLL]), in exynos4_clk_init()
1355 clk_hw_get_rate(hws[CLK_SCLK_VPLL]), in exynos4_clk_init()
1356 clk_hw_get_rate(hws[CLK_DIV_CORE2])); in exynos4_clk_init()
Dclk-s3c64xx.c464 clk_hw_get_rate(hws[MOUT_APLL]), in s3c64xx_clk_init()
465 clk_hw_get_rate(hws[MOUT_MPLL]), in s3c64xx_clk_init()
466 clk_hw_get_rate(hws[MOUT_EPLL]), in s3c64xx_clk_init()
467 clk_hw_get_rate(hws[ARMCLK])); in s3c64xx_clk_init()
Dclk-s5pv210.c794 clk_hw_get_rate(hws[MOUT_APLL]), in __s5pv210_clk_init()
795 clk_hw_get_rate(hws[MOUT_MPLL]), in __s5pv210_clk_init()
796 clk_hw_get_rate(hws[MOUT_EPLL]), in __s5pv210_clk_init()
797 clk_hw_get_rate(hws[MOUT_VPLL])); in __s5pv210_clk_init()
Dclk-cpu.c153 unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent); in exynos_cpuclk_pre_rate_change()
281 unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent); in exynos5433_cpuclk_pre_rate_change()
Dclk-s3c2410.c343 if (clk_hw_get_rate(hws[XTI]) == 12 * MHZ) { in s3c2410_common_clk_init()
353 if (clk_hw_get_rate(hws[XTI]) == 12 * MHZ) { in s3c2410_common_clk_init()
Dclk-exynos5250.c809 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) { in exynos5250_clk_init()
814 if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24 * MHZ) in exynos5250_clk_init()
861 clk_hw_get_rate(hws[CLK_DIV_ARM2])); in exynos5250_clk_init()
/drivers/clk/
Dclk-lan966x.c145 if (clk_hw_get_rate(parent) / req->rate <= DIV_MAX) { in lan966x_gck_determine_rate()
147 req->best_parent_rate = clk_hw_get_rate(parent); in lan966x_gck_determine_rate()
/drivers/clk/bcm/
Dclk-kona.c1007 return clk_hw_get_rate(hw); in kona_peri_clk_round_rate()
1044 parent_rate = clk_hw_get_rate(current_parent); in kona_peri_clk_determine_rate()
1059 parent_rate = clk_hw_get_rate(parent); in kona_peri_clk_determine_rate()
1134 if (rate == clk_hw_get_rate(hw)) in kona_peri_clk_set_rate()

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