Searched refs:gen_synth0_1_parents (Results 1 – 2 of 2) sorted by relevance
| /drivers/clk/spear/ |
| D | spear1340_clock.c | 435 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk", variable
891 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, in spear1340_clk_init()
892 ARRAY_SIZE(gen_synth0_1_parents), in spear1340_clk_init()
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| D | spear1310_clock.c | 368 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk", variable
806 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, in spear1310_clk_init()
807 ARRAY_SIZE(gen_synth0_1_parents), in spear1310_clk_init()
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