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Searched refs:ih_rb_cntl (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dnavi10_ih.c57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in navi10_ih_init_register_offset()
70 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); in navi10_ih_init_register_offset()
81 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); in navi10_ih_init_register_offset()
108 u32 ih_cntl, ih_rb_cntl; in force_update_wptr_for_self_int() local
114 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in force_update_wptr_for_self_int()
120 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, in force_update_wptr_for_self_int()
124 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl)) in force_update_wptr_for_self_int()
127 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in force_update_wptr_for_self_int()
130 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); in force_update_wptr_for_self_int()
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, in force_update_wptr_for_self_int()
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Dtonga_ih.c62 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in tonga_ih_enable_interrupts() local
64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in tonga_ih_enable_interrupts()
65 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in tonga_ih_enable_interrupts()
66 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in tonga_ih_enable_interrupts()
79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in tonga_ih_disable_interrupts() local
81 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in tonga_ih_disable_interrupts()
82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in tonga_ih_disable_interrupts()
83 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in tonga_ih_disable_interrupts()
104 u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr; in tonga_ih_irq_init() local
126 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in tonga_ih_irq_init()
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Dih_v6_0.c56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); in ih_v6_0_init_register_offset()
69 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1); in ih_v6_0_init_register_offset()
96 u32 ih_cntl, ih_rb_cntl; in force_update_wptr_for_self_int() local
99 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1); in force_update_wptr_for_self_int()
105 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, in force_update_wptr_for_self_int()
109 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl)) in force_update_wptr_for_self_int()
112 WREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1, ih_rb_cntl); in force_update_wptr_for_self_int()
136 tmp = RREG32(ih_regs->ih_rb_cntl); in ih_v6_0_toggle_ring_interrupts()
146 WREG32(ih_regs->ih_rb_cntl, tmp); in ih_v6_0_toggle_ring_interrupts()
187 static uint32_t ih_v6_0_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) in ih_v6_0_rb_cntl() argument
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Dvega10_ih.c55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_init_register_offset()
68 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega10_ih_init_register_offset()
79 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); in vega10_ih_init_register_offset()
105 tmp = RREG32(ih_regs->ih_rb_cntl); in vega10_ih_toggle_ring_interrupts()
117 WREG32(ih_regs->ih_rb_cntl, tmp); in vega10_ih_toggle_ring_interrupts()
158 static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) in vega10_ih_rb_cntl() argument
162 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega10_ih_rb_cntl()
164 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega10_ih_rb_cntl()
166 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega10_ih_rb_cntl()
168 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in vega10_ih_rb_cntl()
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Dcz_ih.c63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_enable_interrupts() local
66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in cz_ih_enable_interrupts()
68 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cz_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_disable_interrupts() local
84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in cz_ih_disable_interrupts()
86 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cz_ih_disable_interrupts()
109 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cz_ih_irq_init() local
130 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in cz_ih_irq_init()
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in cz_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
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Diceland_ih.c63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_enable_interrupts() local
66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in iceland_ih_enable_interrupts()
68 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in iceland_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_disable_interrupts() local
84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in iceland_ih_disable_interrupts()
86 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in iceland_ih_disable_interrupts()
110 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in iceland_ih_irq_init() local
130 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in iceland_ih_irq_init()
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in iceland_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
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Dvega20_ih.c58 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega20_ih_init_register_offset()
71 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega20_ih_init_register_offset()
82 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); in vega20_ih_init_register_offset()
108 tmp = RREG32(ih_regs->ih_rb_cntl); in vega20_ih_toggle_ring_interrupts()
121 WREG32(ih_regs->ih_rb_cntl, tmp); in vega20_ih_toggle_ring_interrupts()
162 static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) in vega20_ih_rb_cntl() argument
166 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega20_ih_rb_cntl()
168 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega20_ih_rb_cntl()
170 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega20_ih_rb_cntl()
172 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in vega20_ih_rb_cntl()
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Dcik_ih.c63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_enable_interrupts() local
66 ih_rb_cntl |= IH_RB_CNTL__RB_ENABLE_MASK; in cik_ih_enable_interrupts()
68 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cik_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_disable_interrupts() local
84 ih_rb_cntl &= ~IH_RB_CNTL__RB_ENABLE_MASK; in cik_ih_disable_interrupts()
86 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cik_ih_disable_interrupts()
110 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cik_ih_irq_init() local
129 ih_rb_cntl = (IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK | in cik_ih_irq_init()
133 ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK; in cik_ih_irq_init()
139 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cik_ih_irq_init()
Dsi_ih.c38 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_enable_interrupts() local
41 ih_rb_cntl |= IH_RB_ENABLE; in si_ih_enable_interrupts()
43 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_enable_interrupts()
49 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_disable_interrupts() local
52 ih_rb_cntl &= ~IH_RB_ENABLE; in si_ih_disable_interrupts()
54 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_disable_interrupts()
66 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in si_ih_irq_init() local
79 ih_rb_cntl = IH_WPTR_OVERFLOW_ENABLE | in si_ih_irq_init()
86 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_irq_init()
Damdgpu_ih.h36 uint32_t ih_rb_cntl; member
/drivers/gpu/drm/radeon/
Dr600.c3593 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_enable_interrupts() local
3596 ih_rb_cntl |= IH_RB_ENABLE; in r600_enable_interrupts()
3598 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_enable_interrupts()
3604 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_disable_interrupts() local
3607 ih_rb_cntl &= ~IH_RB_ENABLE; in r600_disable_interrupts()
3609 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_disable_interrupts()
3675 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in r600_irq_init() local
3710 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | in r600_irq_init()
3715 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; in r600_irq_init()
3721 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_irq_init()
Dsi.c5922 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_enable_interrupts() local
5925 ih_rb_cntl |= IH_RB_ENABLE; in si_enable_interrupts()
5927 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_enable_interrupts()
5933 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_disable_interrupts() local
5936 ih_rb_cntl &= ~IH_RB_ENABLE; in si_disable_interrupts()
5938 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_disable_interrupts()
5981 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in si_irq_init() local
6013 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | in si_irq_init()
6018 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; in si_irq_init()
6024 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_irq_init()
Dcik.c6815 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_enable_interrupts() local
6818 ih_rb_cntl |= IH_RB_ENABLE; in cik_enable_interrupts()
6820 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_enable_interrupts()
6833 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_disable_interrupts() local
6836 ih_rb_cntl &= ~IH_RB_ENABLE; in cik_disable_interrupts()
6838 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_disable_interrupts()
6939 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cik_irq_init() local
6971 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | in cik_irq_init()
6976 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; in cik_irq_init()
6982 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_irq_init()