Home
last modified time | relevance | path

Searched refs:mmJPEG_CGC_GATE (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Djpeg_v3_0.c237 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v3_0_disable_clock_gating()
243 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); in jpeg_v3_0_disable_clock_gating()
257 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v3_0_enable_clock_gating()
263 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); in jpeg_v3_0_enable_clock_gating()
Djpeg_v2_0.c273 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v2_0_disable_clock_gating()
279 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); in jpeg_v2_0_disable_clock_gating()
296 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v2_0_enable_clock_gating()
302 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); in jpeg_v2_0_enable_clock_gating()
Djpeg_v2_5.c277 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); in jpeg_v2_5_disable_clock_gating()
282 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); in jpeg_v2_5_disable_clock_gating()
296 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); in jpeg_v2_5_enable_clock_gating()
302 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); in jpeg_v2_5_enable_clock_gating()
Dvcn_v1_0.c464 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); in vcn_v1_0_disable_clock_gating()
466 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); in vcn_v1_0_disable_clock_gating()
588 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); in vcn_v1_0_enable_clock_gating()
590 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); in vcn_v1_0_enable_clock_gating()
652 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_offset.h138 #define mmJPEG_CGC_GATE … macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h298 #define mmJPEG_CGC_GATE … macro
Dvcn_2_5_offset.h363 #define mmJPEG_CGC_GATE … macro
Dvcn_2_0_0_offset.h348 #define mmJPEG_CGC_GATE … macro
Dvcn_3_0_0_offset.h631 #define mmJPEG_CGC_GATE … macro