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Searched refs:mmUVD_CGC_CTRL (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c679 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_set_sw_clock_gating()
718 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_set_sw_clock_gating()
773 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg()
776 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()
782 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg()
785 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()
850 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_get_clockgating_state()
Duvd_v3_1.c213 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_set_dcm()
229 WREG32(mmUVD_CGC_CTRL, tmp); in uvd_v3_1_set_dcm()
607 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_enable_mgcg()
610 WREG32(mmUVD_CGC_CTRL, data); in uvd_v3_1_enable_mgcg()
616 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_enable_mgcg()
619 WREG32(mmUVD_CGC_CTRL, data); in uvd_v3_1_enable_mgcg()
Duvd_v4_2.c614 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
617 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
623 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
626 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
637 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_set_dcm()
653 WREG32(mmUVD_CGC_CTRL, tmp); in uvd_v4_2_set_dcm()
Duvd_v6_0.c1336 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_set_sw_clock_gating()
1376 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_set_sw_clock_gating()
1433 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg()
1436 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg()
1442 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg()
1445 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg()
1515 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_get_clockgating_state()
Dvcn_v2_0.c495 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
502 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
527 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
548 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
625 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
655 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
662 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
664 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
685 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
Dvcn_v1_0.c469 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
477 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
502 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
523 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
593 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
600 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
602 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
623 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
681 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
Dvcn_v2_5.c562 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
569 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
597 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
618 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
696 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
727 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
734 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
736 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
756 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
Dvcn_v3_0.c700 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
707 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
735 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
756 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
856 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
884 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
891 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
893 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
914 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
Duvd_v7_0.c862 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), in uvd_v7_0_sriov_start()
975 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, in uvd_v7_0_start()
1613 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1659 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h34 #define mmUVD_CGC_CTRL 0x3D2C macro
Duvd_4_2_d.h44 #define mmUVD_CGC_CTRL 0x3d2c macro
Duvd_3_1_d.h44 #define mmUVD_CGC_CTRL 0x3d2c macro
Duvd_5_0_d.h50 #define mmUVD_CGC_CTRL 0x3d2c macro
Duvd_6_0_d.h66 #define mmUVD_CGC_CTRL 0x3d2c macro
Duvd_7_0_offset.h146 #define mmUVD_CGC_CTRL … macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h308 #define mmUVD_CGC_CTRL … macro
Dvcn_2_5_offset.h501 #define mmUVD_CGC_CTRL … macro
Dvcn_2_0_0_offset.h508 #define mmUVD_CGC_CTRL … macro
Dvcn_3_0_0_offset.h817 #define mmUVD_CGC_CTRL … macro