| /drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 70 #define mmUVD_RBC_RB_CNTL 0x3DA9 macro
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| D | uvd_4_2_d.h | 74 #define mmUVD_RBC_RB_CNTL 0x3da9 macro
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| D | uvd_3_1_d.h | 76 #define mmUVD_RBC_RB_CNTL 0x3da9 macro
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| D | uvd_5_0_d.h | 80 #define mmUVD_RBC_RB_CNTL 0x3da9 macro
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| D | uvd_6_0_d.h | 96 #define mmUVD_RBC_RB_CNTL 0x3da9 macro
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| D | uvd_7_0_offset.h | 204 #define mmUVD_RBC_RB_CNTL … macro
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v3_1.c | 414 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v3_1_start()
435 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v3_1_start()
452 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v3_1_stop()
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| D | uvd_v4_2.c | 372 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v4_2_start()
393 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v4_2_start()
410 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v4_2_stop()
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| D | uvd_v5_0.c | 424 WREG32(mmUVD_RBC_RB_CNTL, tmp); in uvd_v5_0_start()
444 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); in uvd_v5_0_start()
459 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v5_0_stop()
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| D | uvd_v7_0.c | 915 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); in uvd_v7_0_sriov_start()
1086 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp); in uvd_v7_0_start()
1108 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0, in uvd_v7_0_start()
1143 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v7_0_stop()
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| D | vcn_v1_0.c | 914 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); in vcn_v1_0_start_spg_mode()
938 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, in vcn_v1_0_start_spg_mode()
1072 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); in vcn_v1_0_start_dpg_mode()
1096 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, in vcn_v1_0_start_dpg_mode()
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| D | vcn_v2_0.c | 892 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_0_start_dpg_mode()
1064 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_0_start()
1980 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); in vcn_v2_0_start_sriov()
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| D | vcn_v2_5.c | 879 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_5_start_dpg_mode()
1071 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_5_start()
1291 SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp); in vcn_v2_5_sriov_start()
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| D | uvd_v6_0.c | 839 WREG32(mmUVD_RBC_RB_CNTL, tmp); in uvd_v6_0_start()
890 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v6_0_stop()
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| D | vcn_v3_0.c | 1049 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); in vcn_v3_0_start_dpg_mode()
1236 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); in vcn_v3_0_start()
1422 mmUVD_RBC_RB_CNTL), in vcn_v3_0_start_sriov()
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| /drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 390 #define mmUVD_RBC_RB_CNTL … macro
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| D | vcn_2_5_offset.h | 785 #define mmUVD_RBC_RB_CNTL … macro
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| D | vcn_2_0_0_offset.h | 690 #define mmUVD_RBC_RB_CNTL … macro
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| D | vcn_3_0_0_offset.h | 1169 #define mmUVD_RBC_RB_CNTL … macro
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