| /drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_5_0_d.h | 91 #define mmUVD_SUVD_CGC_CTRL 0x3be6 macro
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| D | uvd_6_0_d.h | 107 #define mmUVD_SUVD_CGC_CTRL 0x3be6 macro
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| D | uvd_7_0_offset.h | 68 #define mmUVD_SUVD_CGC_CTRL … macro
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v5_0.c | 680 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); in uvd_v5_0_set_sw_clock_gating()
719 WREG32(mmUVD_SUVD_CGC_CTRL, data2); in uvd_v5_0_set_sw_clock_gating()
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| D | vcn_v2_0.c | 578 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
589 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
637 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
687 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
698 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
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| D | vcn_v1_0.c | 553 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
564 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
625 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
636 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
690 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
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| D | vcn_v2_5.c | 648 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
659 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
708 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
758 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
769 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
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| D | vcn_v3_0.c | 800 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
820 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
868 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
916 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
936 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
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| D | uvd_v6_0.c | 1337 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); in uvd_v6_0_set_sw_clock_gating()
1377 WREG32(mmUVD_SUVD_CGC_CTRL, data2); in uvd_v6_0_set_sw_clock_gating()
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| D | uvd_v7_0.c | 1615 data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);
1662 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);
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| /drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 158 #define mmUVD_SUVD_CGC_CTRL … macro
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| D | vcn_2_5_offset.h | 509 #define mmUVD_SUVD_CGC_CTRL … macro
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| D | vcn_2_0_0_offset.h | 822 #define mmUVD_SUVD_CGC_CTRL … macro
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| D | vcn_3_0_0_offset.h | 825 #define mmUVD_SUVD_CGC_CTRL … macro
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