| /drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 91 #define mmUVD_VCPU_CACHE_SIZE0 0x3D37 macro
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| D | uvd_4_2_d.h | 61 #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 macro
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| D | uvd_3_1_d.h | 63 #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 macro
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| D | uvd_5_0_d.h | 67 #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 macro
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| D | uvd_6_0_d.h | 83 #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 macro
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| D | uvd_7_0_offset.h | 180 #define mmUVD_VCPU_CACHE_SIZE0 … macro
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| /drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 366 #define mmUVD_VCPU_CACHE_SIZE0 … macro
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| D | vcn_2_5_offset.h | 687 #define mmUVD_VCPU_CACHE_SIZE0 … macro
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| D | vcn_2_0_0_offset.h | 616 #define mmUVD_VCPU_CACHE_SIZE0 … macro
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| D | vcn_3_0_0_offset.h | 1063 #define mmUVD_VCPU_CACHE_SIZE0 … macro
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v2_0.c | 354 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v2_0_mc_resume()
424 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
427 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1913 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), in vcn_v2_0_start_sriov()
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| D | vcn_v2_5.c | 421 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v2_5_mc_resume()
490 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
493 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1226 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0), in vcn_v2_5_sriov_start()
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| D | vcn_v3_0.c | 467 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v3_0_mc_resume()
535 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
538 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1358 mmUVD_VCPU_CACHE_SIZE0), in vcn_v3_0_start_sriov()
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| D | uvd_v3_1.c | 249 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v3_1_mc_resume()
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| D | uvd_v4_2.c | 578 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v4_2_mc_resume()
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| D | uvd_v5_0.c | 290 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v5_0_mc_resume()
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| D | uvd_v7_0.c | 698 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v7_0_mc_resume()
841 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size); in uvd_v7_0_sriov_start()
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| D | vcn_v1_0.c | 325 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v1_0_mc_resume_spg_mode()
395 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
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| D | uvd_v6_0.c | 614 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v6_0_mc_resume()
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