| /drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_hw_sequencer.c | 55 struct pipe_ctx *pipe_ctx = NULL; in dce60_should_enable_fbc() local
71 if (res_ctx->pipe_ctx[i].stream) { in dce60_should_enable_fbc()
73 pipe_ctx = &res_ctx->pipe_ctx[i]; in dce60_should_enable_fbc()
75 if (!pipe_ctx) in dce60_should_enable_fbc()
79 if (pipe_ctx->pipe_idx != underlay_idx) { in dce60_should_enable_fbc()
89 if (!pipe_ctx->stream->link) in dce60_should_enable_fbc()
93 if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) in dce60_should_enable_fbc()
97 if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled) in dce60_should_enable_fbc()
101 if (!pipe_ctx->plane_state) in dce60_should_enable_fbc()
105 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in dce60_should_enable_fbc()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.h | 36 int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);
39 struct pipe_ctx *pipe_ctx,
42 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
44 struct pipe_ctx *pipe_ctx,
55 struct pipe_ctx *pipe,
57 void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);
60 struct pipe_ctx *pipe_ctx,
62 void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
65 struct pipe_ctx *pipe_ctx,
69 bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
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| D | dcn10_hw_sequencer.c | 99 struct pipe_ctx *pipe_ctx; in dcn10_lock_all_pipes() local
104 pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
105 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
111 if (pipe_ctx->top_pipe || in dcn10_lock_all_pipes()
112 !pipe_ctx->stream || in dcn10_lock_all_pipes()
113 !pipe_ctx->plane_state || in dcn10_lock_all_pipes()
118 dc->hwss.pipe_control_lock(dc, pipe_ctx, true); in dcn10_lock_all_pipes()
120 dc->hwss.pipe_control_lock(dc, pipe_ctx, false); in dcn10_lock_all_pipes()
535 bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx) in dcn10_did_underflow_occur() argument
537 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_did_underflow_occur()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | hw_sequencer.h | 35 struct pipe_ctx;
62 void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
63 void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank);
74 struct pipe_ctx *pipe_ctx);
79 struct pipe_ctx *pipe_ctx);
84 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer);
85 void (*update_pending_status)(struct pipe_ctx *pipe_ctx);
91 struct pipe_ctx *pipe, bool lock);
94 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx,
96 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock);
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| D | hw_sequencer_private.h | 54 struct pipe_ctx;
75 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
76 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
80 struct pipe_ctx *pipe_ctx);
82 struct pipe_ctx *pipe_ctx);
83 void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
85 struct pipe_ctx *pipe_ctx,
88 struct pipe_ctx *pipe_ctx,
98 struct pipe_ctx *pipe_ctx,
101 struct pipe_ctx *pipe_ctx,
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_hw_sequencer.c | 283 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, in dce110_set_input_transfer_func() argument
286 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; in dce110_set_input_transfer_func()
611 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, in dce110_set_output_transfer_func() argument
614 struct transform *xfm = pipe_ctx->plane_res.xfm; in dce110_set_output_transfer_func()
636 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) in dce110_update_info_frame() argument
641 ASSERT(pipe_ctx->stream); in dce110_update_info_frame()
643 if (pipe_ctx->stream_res.stream_enc == NULL) in dce110_update_info_frame()
646 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); in dce110_update_info_frame()
647 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); in dce110_update_info_frame()
653 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dce110_update_info_frame()
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| D | dce110_hw_sequencer.h | 43 void dce110_enable_stream(struct pipe_ctx *pipe_ctx);
45 void dce110_disable_stream(struct pipe_ctx *pipe_ctx);
47 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
50 void dce110_blank_stream(struct pipe_ctx *pipe_ctx);
52 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);
53 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);
55 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);
57 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
88 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,
91 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx);
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hwseq.h | 32 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
34 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
41 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
42 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
43 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
45 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
48 struct pipe_ctx *pipe_ctx,
52 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx);
53 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
55 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
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| D | dcn20_hwseq.c | 100 struct pipe_ctx *pipe_ctx, in dcn20_setup_gsl_group_as_lock() argument
112 if (pipe_ctx->stream_res.gsl_group > 0) in dcn20_setup_gsl_group_as_lock()
117 pipe_ctx->stream_res.gsl_group = group_idx; in dcn20_setup_gsl_group_as_lock()
139 group_idx = pipe_ctx->stream_res.gsl_group; in dcn20_setup_gsl_group_as_lock()
143 pipe_ctx->stream_res.gsl_group = 0; in dcn20_setup_gsl_group_as_lock()
167 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && in dcn20_setup_gsl_group_as_lock()
168 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { in dcn20_setup_gsl_group_as_lock()
169 pipe_ctx->stream_res.tg->funcs->set_gsl( in dcn20_setup_gsl_group_as_lock()
170 pipe_ctx->stream_res.tg, in dcn20_setup_gsl_group_as_lock()
173 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( in dcn20_setup_gsl_group_as_lock()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_resource.c | 601 const struct pipe_ctx *pipe_with_clk_src, in is_sharable_clk_src()
602 const struct pipe_ctx *pipe) in is_sharable_clk_src()
633 struct pipe_ctx *pipe_ctx) in resource_find_used_clk_src_for_sharing() argument
638 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) in resource_find_used_clk_src_for_sharing()
639 return res_ctx->pipe_ctx[i].clock_source; in resource_find_used_clk_src_for_sharing()
721 int get_num_mpc_splits(struct pipe_ctx *pipe) in get_num_mpc_splits()
724 struct pipe_ctx *other_pipe = pipe->bottom_pipe; in get_num_mpc_splits()
739 int get_num_odm_splits(struct pipe_ctx *pipe) in get_num_odm_splits()
742 struct pipe_ctx *next_pipe = pipe->next_odm_pipe; in get_num_odm_splits()
755 static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split… in calculate_split_count_and_index() argument
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| D | dc_link.c | 890 struct pipe_ctx *pipe_ctx; in set_all_streams_dpms_off_for_link() local
899 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; in set_all_streams_dpms_off_for_link()
900 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off && in set_all_streams_dpms_off_for_link()
901 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe) { in set_all_streams_dpms_off_for_link()
902 stream_update.stream = pipe_ctx->stream; in set_all_streams_dpms_off_for_link()
904 pipe_ctx->stream, &stream_update, in set_all_streams_dpms_off_for_link()
1954 static void enable_stream_features(struct pipe_ctx *pipe_ctx) in enable_stream_features() argument
1956 struct dc_stream_state *stream = pipe_ctx->stream; in enable_stream_features()
1958 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { in enable_stream_features()
1984 struct pipe_ctx *pipe_ctx) in enable_link_dp() argument
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| D | dc_hw_sequencer.c | 294 struct pipe_ctx *pipe_ctx, in get_mpctree_visual_confirm_color() argument
306 struct pipe_ctx *top_pipe = pipe_ctx; in get_mpctree_visual_confirm_color()
315 const struct pipe_ctx *pipe_ctx, in get_surface_visual_confirm_color() argument
320 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color()
324 if (pipe_ctx->plane_state->layer_index > 0) { in get_surface_visual_confirm_color()
334 if (pipe_ctx->plane_state->layer_index > 0) { in get_surface_visual_confirm_color()
353 if (pipe_ctx->plane_state->layer_index > 0) { in get_surface_visual_confirm_color()
365 struct pipe_ctx *pipe_ctx, in get_hdr_visual_confirm_color() argument
371 struct pipe_ctx *top_pipe_ctx = pipe_ctx; in get_hdr_visual_confirm_color()
407 struct pipe_ctx *pipe_ctx, in get_subvp_visual_confirm_color() argument
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| D | dc_stream.c | 258 struct pipe_ctx *pipe_to_program = NULL; in program_cursor_attributes()
266 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in program_cursor_attributes() local
268 if (pipe_ctx->stream != stream) in program_cursor_attributes()
272 pipe_to_program = pipe_ctx; in program_cursor_attributes()
278 dc->hwss.set_cursor_attribute(pipe_ctx); in program_cursor_attributes()
280 dc_send_update_cursor_info_to_dmu(pipe_ctx, i); in program_cursor_attributes()
282 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); in program_cursor_attributes()
364 struct pipe_ctx *pipe_to_program = NULL; in program_cursor_position()
372 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in program_cursor_position() local
374 if (pipe_ctx->stream != stream || in program_cursor_position()
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| D | dc.c | 418 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_adjust_vmin_vmax()
453 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_last_used_drr_vtotal()
483 struct pipe_ctx *pipe = in dc_stream_get_crtc_position()
484 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_crtc_position()
503 struct pipe_ctx *pipe; in dc_stream_forward_dmcu_crc_window()
521 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_forward_dmcu_crc_window()
548 struct pipe_ctx *pipe; in dc_stream_stop_dmcu_crc_win_update()
555 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_stop_dmcu_crc_win_update()
598 struct pipe_ctx *pipe; in dc_stream_configure_crc()
603 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_configure_crc()
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| /drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_hwseq.c | 97 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) in update_dsc_on_stream() argument
99 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream()
100 struct dc_stream_state *stream = pipe_ctx->stream; in update_dsc_on_stream()
101 struct pipe_ctx *odm_pipe; in update_dsc_on_stream()
105 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) in update_dsc_on_stream()
118 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; in update_dsc_on_stream()
124 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in update_dsc_on_stream()
125 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { in update_dsc_on_stream()
138 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
139 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, in update_dsc_on_stream()
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| /drivers/gpu/drm/amd/display/dc/basics/ |
| D | dc_common.c | 52 bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) in is_lower_pipe_tree_visible() argument
54 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) in is_lower_pipe_tree_visible()
56 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) in is_lower_pipe_tree_visible()
61 bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx) in is_upper_pipe_tree_visible() argument
63 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) in is_upper_pipe_tree_visible()
65 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) in is_upper_pipe_tree_visible()
70 bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx) in is_pipe_tree_visible() argument
72 if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) in is_pipe_tree_visible()
74 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) in is_pipe_tree_visible()
76 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) in is_pipe_tree_visible()
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| /drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_hwseq.c | 57 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) in patch_address_for_sbs_tb_stereo() argument
59 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
60 bool sec_split = pipe_ctx->top_pipe && in patch_address_for_sbs_tb_stereo()
61 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
64 (pipe_ctx->stream->timing.timing_3d_format == in patch_address_for_sbs_tb_stereo()
66 pipe_ctx->stream->timing.timing_3d_format == in patch_address_for_sbs_tb_stereo()
73 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && in patch_address_for_sbs_tb_stereo()
130 void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) in dcn201_update_plane_addr() argument
134 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in dcn201_update_plane_addr()
142 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); in dcn201_update_plane_addr()
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| D | dcn201_hwseq.h | 31 void dcn201_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);
33 void dcn201_unblank_stream(struct pipe_ctx *pipe_ctx,
35 void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
36 void dcn201_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);
37 void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
38 void dcn201_set_cursor_attribute(struct pipe_ctx *pipe_ctx);
41 struct pipe_ctx *pipe,
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| /drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_hwseq.c | 231 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn32_calculate_cab_allocation()
281 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[j]; in dcn32_calculate_cab_allocation()
452 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn32_commit_subvp_config() local
454 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream && in dcn32_commit_subvp_config()
455 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) { in dcn32_commit_subvp_config()
474 struct pipe_ctx *top_pipe_to_program, in dcn32_subvp_pipe_control_lock()
480 struct pipe_ctx *pipe; in dcn32_subvp_pipe_control_lock()
483 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_pipe_control_lock()
503 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_pipe_control_lock()
520 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) in dcn32_set_mpc_shaper_3dlut() argument
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| D | dcn32_hwseq.h | 50 bool dcn32_set_mcm_luts(struct pipe_ctx *pipe_ctx,
54 struct pipe_ctx *pipe_ctx,
58 struct pipe_ctx *pipe_ctx,
69 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
71 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, uns…
73 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
79 struct pipe_ctx *top_pipe_to_program,
82 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
85 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);
93 struct pipe_ctx *phantom_pipe);
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_hwseq.c | 129 void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx) in dcn21_PLAT_58856_wa() argument
131 if (!pipe_ctx->stream->dpms_off) in dcn21_PLAT_58856_wa()
134 pipe_ctx->stream->dpms_off = false; in dcn21_PLAT_58856_wa()
135 core_link_enable_stream(context, pipe_ctx); in dcn21_PLAT_58856_wa()
136 core_link_disable_stream(pipe_ctx); in dcn21_PLAT_58856_wa()
137 pipe_ctx->stream->dpms_off = true; in dcn21_PLAT_58856_wa()
162 void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) in dcn21_set_abm_immediate_disable() argument
164 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_abm_immediate_disable()
165 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable()
166 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; in dcn21_set_abm_immediate_disable()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hwseq.h | 55 bool dcn30_set_blend_lut(struct pipe_ctx *pipe_ctx,
59 struct pipe_ctx *pipe_ctx,
62 struct pipe_ctx *pipe_ctx,
64 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
65 void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx);
66 void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
76 struct pipe_ctx *pipe_ctx,
84 struct pipe_ctx *pipe_ctx,
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| /drivers/gpu/drm/amd/display/dc/link/ |
| D | link_hwss_hpo_dp.c | 50 static void set_hpo_dp_throttled_vcp_size(struct pipe_ctx *pipe_ctx, in set_hpo_dp_throttled_vcp_size() argument
54 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_throttled_vcp_size()
56 pipe_ctx->link_res.hpo_dp_link_enc; in set_hpo_dp_throttled_vcp_size()
63 static void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx, in set_hpo_dp_hblank_min_symbol_width() argument
68 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_hblank_min_symbol_width()
69 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; in set_hpo_dp_hblank_min_symbol_width()
72 dc_link_bandwidth_kbps(pipe_ctx->stream->link, link_settings); in set_hpo_dp_hblank_min_symbol_width()
90 static int get_odm_segment_count(struct pipe_ctx *pipe_ctx) in get_odm_segment_count() argument
92 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; in get_odm_segment_count()
103 static void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx) in setup_hpo_dp_stream_encoder() argument
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| D | link_hwss_dio.c | 30 void set_dio_throttled_vcp_size(struct pipe_ctx *pipe_ctx, in set_dio_throttled_vcp_size() argument
33 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; in set_dio_throttled_vcp_size()
40 void setup_dio_stream_encoder(struct pipe_ctx *pipe_ctx) in setup_dio_stream_encoder() argument
42 struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); in setup_dio_stream_encoder()
43 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in setup_dio_stream_encoder()
46 pipe_ctx->stream_res.stream_enc->id, true); in setup_dio_stream_encoder()
47 if (dc_is_dp_signal(pipe_ctx->stream->signal)) in setup_dio_stream_encoder()
48 dp_source_sequence_trace(pipe_ctx->stream->link, in setup_dio_stream_encoder()
54 void reset_dio_stream_encoder(struct pipe_ctx *pipe_ctx) in reset_dio_stream_encoder() argument
56 struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); in reset_dio_stream_encoder()
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_hwseq.c | 396 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) in dcn31_update_info_frame() argument
401 ASSERT(pipe_ctx->stream); in dcn31_update_info_frame()
403 if (pipe_ctx->stream_res.stream_enc == NULL) in dcn31_update_info_frame()
406 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); in dcn31_update_info_frame()
407 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); in dcn31_update_info_frame()
413 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dcn31_update_info_frame()
414 pipe_ctx->stream_res.stream_enc, in dcn31_update_info_frame()
415 &pipe_ctx->stream_res.encoder_info_frame); in dcn31_update_info_frame()
417 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( in dcn31_update_info_frame()
418 pipe_ctx->stream_res.stream_enc, in dcn31_update_info_frame()
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