Searched refs:register_access (Results 1 – 3 of 3) sorted by relevance
| /drivers/gpu/drm/tegra/ |
| D | trace.h | 10 DECLARE_EVENT_CLASS(register_access,
27 DEFINE_EVENT(register_access, dc_writel,
30 DEFINE_EVENT(register_access, dc_readl,
34 DEFINE_EVENT(register_access, hdmi_writel,
37 DEFINE_EVENT(register_access, hdmi_readl,
41 DEFINE_EVENT(register_access, dsi_writel,
44 DEFINE_EVENT(register_access, dsi_readl,
48 DEFINE_EVENT(register_access, dpaux_writel,
51 DEFINE_EVENT(register_access, dpaux_readl,
55 DEFINE_EVENT(register_access, sor_writel,
[all …]
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| /drivers/media/platform/nvidia/tegra-vde/ |
| D | trace.h | 13 DECLARE_EVENT_CLASS(register_access,
31 DEFINE_EVENT(register_access, vde_writel,
35 DEFINE_EVENT(register_access, vde_readl,
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| /drivers/mmc/host/ |
| D | vub300.c | 531 *register_access, u8 func) in __add_offloaded_reg_to_fifo()
534 memcpy(&vub300->fn[func].reg[MAXREGMASK & r], register_access, in __add_offloaded_reg_to_fifo()
541 struct offload_registers_access *register_access) in add_offloaded_reg() argument
543 u32 Register = ((0x03 & register_access->command_byte[0]) << 15) in add_offloaded_reg()
544 | ((0xFF & register_access->command_byte[1]) << 7) in add_offloaded_reg()
545 | ((0xFE & register_access->command_byte[2]) >> 1); in add_offloaded_reg()
546 u8 func = ((0x70 & register_access->command_byte[0]) >> 4); in add_offloaded_reg()
555 register_access->Respond_Byte[2]; in add_offloaded_reg()
557 register_access->Respond_Byte[3]; in add_offloaded_reg()
564 __add_offloaded_reg_to_fifo(vub300, register_access, func); in add_offloaded_reg()
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