| /drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_resource.c | 760 struct optc *tgn10 = in dcn201_timing_generator_create() local
763 if (!tgn10) in dcn201_timing_generator_create()
766 tgn10->base.inst = instance; in dcn201_timing_generator_create()
767 tgn10->base.ctx = ctx; in dcn201_timing_generator_create()
769 tgn10->tg_regs = &tg_regs[instance]; in dcn201_timing_generator_create()
770 tgn10->tg_shift = &tg_shift; in dcn201_timing_generator_create()
771 tgn10->tg_mask = &tg_mask; in dcn201_timing_generator_create()
773 dcn201_timing_generator_init(tgn10); in dcn201_timing_generator_create()
775 return &tgn10->base; in dcn201_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 617 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); in dcn302_timing_generator_create() local
619 if (!tgn10) in dcn302_timing_generator_create()
622 tgn10->base.inst = instance; in dcn302_timing_generator_create()
623 tgn10->base.ctx = ctx; in dcn302_timing_generator_create()
625 tgn10->tg_regs = &optc_regs[instance]; in dcn302_timing_generator_create()
626 tgn10->tg_shift = &optc_shift; in dcn302_timing_generator_create()
627 tgn10->tg_mask = &optc_mask; in dcn302_timing_generator_create()
629 dcn30_timing_generator_init(tgn10); in dcn302_timing_generator_create()
631 return &tgn10->base; in dcn302_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 572 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); in dcn303_timing_generator_create() local
574 if (!tgn10) in dcn303_timing_generator_create()
577 tgn10->base.inst = instance; in dcn303_timing_generator_create()
578 tgn10->base.ctx = ctx; in dcn303_timing_generator_create()
580 tgn10->tg_regs = &optc_regs[instance]; in dcn303_timing_generator_create()
581 tgn10->tg_shift = &optc_shift; in dcn303_timing_generator_create()
582 tgn10->tg_mask = &optc_mask; in dcn303_timing_generator_create()
584 dcn30_timing_generator_init(tgn10); in dcn303_timing_generator_create()
586 return &tgn10->base; in dcn303_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 863 struct optc *tgn10 = in dcn301_timing_generator_create() local
866 if (!tgn10) in dcn301_timing_generator_create()
869 tgn10->base.inst = instance; in dcn301_timing_generator_create()
870 tgn10->base.ctx = ctx; in dcn301_timing_generator_create()
872 tgn10->tg_regs = &optc_regs[instance]; in dcn301_timing_generator_create()
873 tgn10->tg_shift = &optc_shift; in dcn301_timing_generator_create()
874 tgn10->tg_mask = &optc_mask; in dcn301_timing_generator_create()
876 dcn30_timing_generator_init(tgn10); in dcn301_timing_generator_create()
878 return &tgn10->base; in dcn301_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.c | 713 struct optc *tgn10 = in dcn10_timing_generator_create() local
716 if (!tgn10) in dcn10_timing_generator_create()
719 tgn10->base.inst = instance; in dcn10_timing_generator_create()
720 tgn10->base.ctx = ctx; in dcn10_timing_generator_create()
722 tgn10->tg_regs = &tg_regs[instance]; in dcn10_timing_generator_create()
723 tgn10->tg_shift = &tg_shift; in dcn10_timing_generator_create()
724 tgn10->tg_mask = &tg_mask; in dcn10_timing_generator_create()
726 dcn10_timing_generator_init(tgn10); in dcn10_timing_generator_create()
728 return &tgn10->base; in dcn10_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 1080 struct optc *tgn10 = in dcn21_timing_generator_create() local
1083 if (!tgn10) in dcn21_timing_generator_create()
1086 tgn10->base.inst = instance; in dcn21_timing_generator_create()
1087 tgn10->base.ctx = ctx; in dcn21_timing_generator_create()
1089 tgn10->tg_regs = &tg_regs[instance]; in dcn21_timing_generator_create()
1090 tgn10->tg_shift = &tg_shift; in dcn21_timing_generator_create()
1091 tgn10->tg_mask = &tg_mask; in dcn21_timing_generator_create()
1093 dcn20_timing_generator_init(tgn10); in dcn21_timing_generator_create()
1095 return &tgn10->base; in dcn21_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/dcn316/ |
| D | dcn316_resource.c | 1068 struct optc *tgn10 = in dcn31_timing_generator_create() local
1071 if (!tgn10) in dcn31_timing_generator_create()
1074 tgn10->base.inst = instance; in dcn31_timing_generator_create()
1075 tgn10->base.ctx = ctx; in dcn31_timing_generator_create()
1077 tgn10->tg_regs = &optc_regs[instance]; in dcn31_timing_generator_create()
1078 tgn10->tg_shift = &optc_shift; in dcn31_timing_generator_create()
1079 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
1081 dcn31_timing_generator_init(tgn10); in dcn31_timing_generator_create()
1083 return &tgn10->base; in dcn31_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_resource.c | 1120 struct optc *tgn10 = in dcn31_timing_generator_create() local
1123 if (!tgn10) in dcn31_timing_generator_create()
1126 tgn10->base.inst = instance; in dcn31_timing_generator_create()
1127 tgn10->base.ctx = ctx; in dcn31_timing_generator_create()
1129 tgn10->tg_regs = &optc_regs[instance]; in dcn31_timing_generator_create()
1130 tgn10->tg_shift = &optc_shift; in dcn31_timing_generator_create()
1131 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
1133 dcn314_timing_generator_init(tgn10); in dcn31_timing_generator_create()
1135 return &tgn10->base; in dcn31_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/dcn315/ |
| D | dcn315_resource.c | 1072 struct optc *tgn10 = in dcn31_timing_generator_create() local
1075 if (!tgn10) in dcn31_timing_generator_create()
1078 tgn10->base.inst = instance; in dcn31_timing_generator_create()
1079 tgn10->base.ctx = ctx; in dcn31_timing_generator_create()
1081 tgn10->tg_regs = &optc_regs[instance]; in dcn31_timing_generator_create()
1082 tgn10->tg_shift = &optc_shift; in dcn31_timing_generator_create()
1083 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
1085 dcn31_timing_generator_init(tgn10); in dcn31_timing_generator_create()
1087 return &tgn10->base; in dcn31_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/dcn321/ |
| D | dcn321_resource.c | 1002 struct optc *tgn10 = in dcn321_timing_generator_create() local
1005 if (!tgn10) in dcn321_timing_generator_create()
1015 tgn10->base.inst = instance; in dcn321_timing_generator_create()
1016 tgn10->base.ctx = ctx; in dcn321_timing_generator_create()
1018 tgn10->tg_regs = &optc_regs[instance]; in dcn321_timing_generator_create()
1019 tgn10->tg_shift = &optc_shift; in dcn321_timing_generator_create()
1020 tgn10->tg_mask = &optc_mask; in dcn321_timing_generator_create()
1022 dcn32_timing_generator_init(tgn10); in dcn321_timing_generator_create()
1024 return &tgn10->base; in dcn321_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 1073 struct optc *tgn10 = in dcn31_timing_generator_create() local
1076 if (!tgn10) in dcn31_timing_generator_create()
1079 tgn10->base.inst = instance; in dcn31_timing_generator_create()
1080 tgn10->base.ctx = ctx; in dcn31_timing_generator_create()
1082 tgn10->tg_regs = &optc_regs[instance]; in dcn31_timing_generator_create()
1083 tgn10->tg_shift = &optc_shift; in dcn31_timing_generator_create()
1084 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
1086 dcn31_timing_generator_init(tgn10); in dcn31_timing_generator_create()
1088 return &tgn10->base; in dcn31_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 905 struct optc *tgn10 = in dcn30_timing_generator_create() local
908 if (!tgn10) in dcn30_timing_generator_create()
911 tgn10->base.inst = instance; in dcn30_timing_generator_create()
912 tgn10->base.ctx = ctx; in dcn30_timing_generator_create()
914 tgn10->tg_regs = &optc_regs[instance]; in dcn30_timing_generator_create()
915 tgn10->tg_shift = &optc_shift; in dcn30_timing_generator_create()
916 tgn10->tg_mask = &optc_mask; in dcn30_timing_generator_create()
918 dcn30_timing_generator_init(tgn10); in dcn30_timing_generator_create()
920 return &tgn10->base; in dcn30_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_resource.c | 1003 struct optc *tgn10 = in dcn32_timing_generator_create() local
1006 if (!tgn10) in dcn32_timing_generator_create()
1016 tgn10->base.inst = instance; in dcn32_timing_generator_create()
1017 tgn10->base.ctx = ctx; in dcn32_timing_generator_create()
1019 tgn10->tg_regs = &optc_regs[instance]; in dcn32_timing_generator_create()
1020 tgn10->tg_shift = &optc_shift; in dcn32_timing_generator_create()
1021 tgn10->tg_mask = &optc_mask; in dcn32_timing_generator_create()
1023 dcn32_timing_generator_init(tgn10); in dcn32_timing_generator_create()
1025 return &tgn10->base; in dcn32_timing_generator_create()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 897 struct optc *tgn10 = in dcn20_timing_generator_create() local
900 if (!tgn10) in dcn20_timing_generator_create()
903 tgn10->base.inst = instance; in dcn20_timing_generator_create()
904 tgn10->base.ctx = ctx; in dcn20_timing_generator_create()
906 tgn10->tg_regs = &tg_regs[instance]; in dcn20_timing_generator_create()
907 tgn10->tg_shift = &tg_shift; in dcn20_timing_generator_create()
908 tgn10->tg_mask = &tg_mask; in dcn20_timing_generator_create()
910 dcn20_timing_generator_init(tgn10); in dcn20_timing_generator_create()
912 return &tgn10->base; in dcn20_timing_generator_create()
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