Home
last modified time | relevance | path

Searched refs:tiled (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/i915/gvt/
Dfb_decoder.c148 u32 tiled, int stride_mask, int bpp) in intel_vgpu_get_stride() argument
156 switch (tiled) { in intel_vgpu_get_stride()
176 tiled); in intel_vgpu_get_stride()
220 plane->tiled = val & PLANE_CTL_TILED_MASK; in intel_vgpu_decode_primary_plane()
235 plane->tiled = val & DISP_TILED; in intel_vgpu_decode_primary_plane()
259 plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled, in intel_vgpu_decode_primary_plane()
429 plane->tiled = !!(val & SPRITE_TILED); in intel_vgpu_decode_sprite_plane()
Dfb_decoder.h108 u32 tiled; /* tiling mode: linear, X-tiled, Y tiled, etc */ member
123 u8 tiled; /* X-tiled */ member
Ddmabuf.c272 switch (p.tiled) { in vgpu_get_plane_info()
289 gvt_vgpu_err("invalid tiling mode: %x\n", p.tiled); in vgpu_get_plane_info()
/drivers/gpu/drm/omapdrm/
Domap_gem.c1343 tiler_align(gem2fmt(flags), &gsize.tiled.width, in omap_gem_new()
1344 &gsize.tiled.height); in omap_gem_new()
1346 size = tiler_size(gem2fmt(flags), gsize.tiled.width, in omap_gem_new()
1347 gsize.tiled.height); in omap_gem_new()
1349 omap_obj->width = gsize.tiled.width; in omap_gem_new()
1350 omap_obj->height = gsize.tiled.height; in omap_gem_new()
/drivers/gpu/drm/sun4i/
Dsun4i_frontend.c270 bool tiled = (modifier == DRM_FORMAT_MOD_ALLWINNER_TILED); in sun4i_frontend_drm_format_to_input_mode() local
278 *val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_SEMIPLANAR in sun4i_frontend_drm_format_to_input_mode()
283 *val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_PLANAR in sun4i_frontend_drm_format_to_input_mode()
/drivers/gpu/drm/radeon/
Dradeon_fb.c89 int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled) in radeon_align_pitch() argument
92 int align_large = (ASIC_IS_AVIVO(rdev)) || tiled; in radeon_align_pitch()
Dr600_cs.c2380 u32 header, cmd, count, tiled; in r600_dma_cs_parse() local
2396 tiled = GET_DMA_T(header); in r600_dma_cs_parse()
2405 if (tiled) { in r600_dma_cs_parse()
2436 if (tiled) { in r600_dma_cs_parse()
Dradeon_mode.h955 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
/drivers/gpu/drm/exynos/
Dexynos_drm_gsc.c448 static void gsc_src_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled) in gsc_src_set_fmt() argument
514 if (tiled) in gsc_src_set_fmt()
635 static void gsc_dst_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled) in gsc_dst_set_fmt() argument
701 if (tiled) in gsc_dst_set_fmt()
Dexynos_drm_fimc.c364 static void fimc_src_set_fmt(struct fimc_context *ctx, u32 fmt, bool tiled) in fimc_src_set_fmt() argument
406 if (tiled) in fimc_src_set_fmt()
630 static void fimc_dst_set_fmt(struct fimc_context *ctx, u32 fmt, bool tiled) in fimc_dst_set_fmt() argument
679 if (tiled) in fimc_dst_set_fmt()
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_gem.c881 bool tiled) in amdgpu_gem_align_pitch() argument
/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/
Dcom.fuc515 // Setup to handle a tiled surface