| /drivers/gpu/drm/omapdrm/dss/ |
| D | video-pll.c | 28 static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll) in dss_dpll_enable_scp_clk() argument
30 REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_enable_scp_clk()
33 static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll) in dss_dpll_disable_scp_clk() argument
35 REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_disable_scp_clk()
38 static void dss_dpll_power_enable(struct dss_video_pll *vpll) in dss_dpll_power_enable() argument
40 REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */ in dss_dpll_power_enable()
49 static void dss_dpll_power_disable(struct dss_video_pll *vpll) in dss_dpll_power_disable() argument
51 REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */ in dss_dpll_power_disable()
56 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); in dss_video_pll_enable() local
65 dss_dpll_enable_scp_clk(vpll); in dss_video_pll_enable()
[all …]
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| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | video-pll.c | 30 static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll) in dss_dpll_enable_scp_clk() argument
32 REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_enable_scp_clk()
35 static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll) in dss_dpll_disable_scp_clk() argument
37 REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_disable_scp_clk()
40 static void dss_dpll_power_enable(struct dss_video_pll *vpll) in dss_dpll_power_enable() argument
42 REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */ in dss_dpll_power_enable()
51 static void dss_dpll_power_disable(struct dss_video_pll *vpll) in dss_dpll_power_disable() argument
53 REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */ in dss_dpll_power_disable()
58 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); in dss_video_pll_enable() local
67 dss_dpll_enable_scp_clk(vpll); in dss_video_pll_enable()
[all …]
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| /drivers/mfd/ |
| D | stw481x.c | 82 u8 vpll; in stw481x_startup() local
113 vpll = (ret >> 4) & 1; /* Save bit 4 */ in stw481x_startup()
118 vpll |= (ret >> 1) & 2; in stw481x_startup()
125 vpll_val[vpll] / 100, vpll_val[vpll] % 100, in stw481x_startup()
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| /drivers/clk/samsung/ |
| D | clk-s5pv210.c | 71 vpll, enumerator
722 [vpll] = PLL(pll_4502, FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
734 [vpll] = PLL(pll_4500, FOUT_VPLL, "fout_vpll", "fin_pll",
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| D | clk-exynos4.c | 146 apll, mpll, epll, vpll, enumerator
1153 [vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
1164 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
1275 exynos4210_plls[vpll].rate_table = in exynos4_clk_init()
1286 exynos4x12_plls[vpll].rate_table = in exynos4_clk_init()
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| D | clk-exynos5250.c | 105 apll, mpll, cpll, epll, vpll, gpll, bpll, enumerator
745 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
815 exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl; in exynos5250_clk_init()
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| D | clk-exynos5420.c | 150 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, enumerator
1476 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
1601 exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl; in exynos5x_clk_init()
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| /drivers/video/fbdev/nvidia/ |
| D | nv_type.h | 71 u32 vpll; member
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| D | nvidia.c | 431 state->vpll = state->pll; in nvidia_calc_regs()
444 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508); in nvidia_calc_regs()
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| D | nv_hw.c | 1592 NV_WR32(par->PRAMDAC0, 0x0508, state->vpll); in NVLoadStateExt()
1644 state->vpll = NV_RD32(par->PRAMDAC0, 0x0508); in NVUnloadStateExt()
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| /drivers/video/fbdev/riva/ |
| D | riva_hw.h | 509 U032 vpll; member
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| D | riva_hw.c | 1308 state->vpll = (p << 16) | (n << 8) | m; in CalcStateExt()
1674 NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll); in LoadStateExt()
1734 state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508); in UnloadStateExt()
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| D | fbdev.c | 798 newmode.ext.vpll2 = newmode.ext.vpll; in riva_load_video_mode()
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| /drivers/regulator/ |
| D | mc13892-regulator.c | 273 MC13892_DEFINE_REGU(VPLL, vpll, REGULATORMODE0, REGULATORSETTING0,
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| /drivers/clk/rockchip/ |
| D | clk-rk3399.c | 19 lpll, bpll, dpll, cpll, gpll, npll, vpll, enumerator
231 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
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| D | clk-rk3568.c | 23 apll, dpll, gpll, cpll, npll, vpll, enumerator
337 [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p,
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