1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Driver Header File for FPGA Device Feature List (DFL) Support
4 *
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
6 *
7 * Authors:
8 * Kang Luwei <luwei.kang@intel.com>
9 * Zhang Yi <yi.z.zhang@intel.com>
10 * Wu Hao <hao.wu@intel.com>
11 * Xiao Guangrong <guangrong.xiao@linux.intel.com>
12 */
13
14 #ifndef __FPGA_DFL_H
15 #define __FPGA_DFL_H
16
17 #include <linux/bitfield.h>
18 #include <linux/cdev.h>
19 #include <linux/delay.h>
20 #include <linux/eventfd.h>
21 #include <linux/fs.h>
22 #include <linux/interrupt.h>
23 #include <linux/iopoll.h>
24 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <linux/mod_devicetable.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/uuid.h>
29 #include <linux/fpga/fpga-region.h>
30
31 /* maximum supported number of ports */
32 #define MAX_DFL_FPGA_PORT_NUM 4
33 /* plus one for fme device */
34 #define MAX_DFL_FEATURE_DEV_NUM (MAX_DFL_FPGA_PORT_NUM + 1)
35
36 /* Reserved 0xfe for Header Group Register and 0xff for AFU */
37 #define FEATURE_ID_FIU_HEADER 0xfe
38 #define FEATURE_ID_AFU 0xff
39
40 #define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
41 #define FME_FEATURE_ID_THERMAL_MGMT 0x1
42 #define FME_FEATURE_ID_POWER_MGMT 0x2
43 #define FME_FEATURE_ID_GLOBAL_IPERF 0x3
44 #define FME_FEATURE_ID_GLOBAL_ERR 0x4
45 #define FME_FEATURE_ID_PR_MGMT 0x5
46 #define FME_FEATURE_ID_HSSI 0x6
47 #define FME_FEATURE_ID_GLOBAL_DPERF 0x7
48
49 #define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
50 #define PORT_FEATURE_ID_AFU FEATURE_ID_AFU
51 #define PORT_FEATURE_ID_ERROR 0x10
52 #define PORT_FEATURE_ID_UMSG 0x11
53 #define PORT_FEATURE_ID_UINT 0x12
54 #define PORT_FEATURE_ID_STP 0x13
55
56 /*
57 * Device Feature Header Register Set
58 *
59 * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers.
60 * For AFUs, they have DFH + GUID as common header registers.
61 * For private features, they only have DFH register as common header.
62 */
63 #define DFH 0x0
64 #define GUID_L 0x8
65 #define GUID_H 0x10
66 #define NEXT_AFU 0x18
67
68 #define DFH_SIZE 0x8
69
70 /* Device Feature Header Register Bitfield */
71 #define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */
72 #define DFH_ID_FIU_FME 0
73 #define DFH_ID_FIU_PORT 1
74 #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
75 #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
76 #define DFH_EOL BIT_ULL(40) /* End of list */
77 #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
78 #define DFH_TYPE_AFU 1
79 #define DFH_TYPE_PRIVATE 3
80 #define DFH_TYPE_FIU 4
81
82 /* Next AFU Register Bitfield */
83 #define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */
84
85 /* FME Header Register Set */
86 #define FME_HDR_DFH DFH
87 #define FME_HDR_GUID_L GUID_L
88 #define FME_HDR_GUID_H GUID_H
89 #define FME_HDR_NEXT_AFU NEXT_AFU
90 #define FME_HDR_CAP 0x30
91 #define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8))
92 #define FME_PORT_OFST_BAR_SKIP 7
93 #define FME_HDR_BITSTREAM_ID 0x60
94 #define FME_HDR_BITSTREAM_MD 0x68
95
96 /* FME Fab Capability Register Bitfield */
97 #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */
98 #define FME_CAP_SOCKET_ID BIT_ULL(8) /* Socket ID */
99 #define FME_CAP_PCIE0_LINK_AVL BIT_ULL(12) /* PCIE0 Link */
100 #define FME_CAP_PCIE1_LINK_AVL BIT_ULL(13) /* PCIE1 Link */
101 #define FME_CAP_COHR_LINK_AVL BIT_ULL(14) /* Coherent Link */
102 #define FME_CAP_IOMMU_AVL BIT_ULL(16) /* IOMMU available */
103 #define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */
104 #define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */
105 #define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */
106 #define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */
107
108 /* FME Port Offset Register Bitfield */
109 /* Offset to port device feature header */
110 #define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0)
111 /* PCI Bar ID for this port */
112 #define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32)
113 /* AFU MMIO access permission. 1 - VF, 0 - PF. */
114 #define FME_PORT_OFST_ACC_CTRL BIT_ULL(55)
115 #define FME_PORT_OFST_ACC_PF 0
116 #define FME_PORT_OFST_ACC_VF 1
117 #define FME_PORT_OFST_IMP BIT_ULL(60)
118
119 /* FME Error Capability Register */
120 #define FME_ERROR_CAP 0x70
121
122 /* FME Error Capability Register Bitfield */
123 #define FME_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */
124 #define FME_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */
125
126 /* PORT Header Register Set */
127 #define PORT_HDR_DFH DFH
128 #define PORT_HDR_GUID_L GUID_L
129 #define PORT_HDR_GUID_H GUID_H
130 #define PORT_HDR_NEXT_AFU NEXT_AFU
131 #define PORT_HDR_CAP 0x30
132 #define PORT_HDR_CTRL 0x38
133 #define PORT_HDR_STS 0x40
134 #define PORT_HDR_USRCLK_CMD0 0x50
135 #define PORT_HDR_USRCLK_CMD1 0x58
136 #define PORT_HDR_USRCLK_STS0 0x60
137 #define PORT_HDR_USRCLK_STS1 0x68
138
139 /* Port Capability Register Bitfield */
140 #define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */
141 #define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */
142 #define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */
143
144 /* Port Control Register Bitfield */
145 #define PORT_CTRL_SFTRST BIT_ULL(0) /* Port soft reset */
146 /* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/
147 #define PORT_CTRL_LATENCY BIT_ULL(2)
148 #define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */
149
150 /* Port Status Register Bitfield */
151 #define PORT_STS_AP2_EVT BIT_ULL(13) /* AP2 event detected */
152 #define PORT_STS_AP1_EVT BIT_ULL(12) /* AP1 event detected */
153 #define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */
154 #define PORT_STS_PWR_STATE_NORM 0
155 #define PORT_STS_PWR_STATE_AP1 1 /* 50% throttling */
156 #define PORT_STS_PWR_STATE_AP2 2 /* 90% throttling */
157 #define PORT_STS_PWR_STATE_AP6 6 /* 100% throttling */
158
159 /* Port Error Capability Register */
160 #define PORT_ERROR_CAP 0x38
161
162 /* Port Error Capability Register Bitfield */
163 #define PORT_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */
164 #define PORT_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */
165
166 /* Port Uint Capability Register */
167 #define PORT_UINT_CAP 0x8
168
169 /* Port Uint Capability Register Bitfield */
170 #define PORT_UINT_CAP_INT_NUM GENMASK_ULL(11, 0) /* Interrupts num */
171 #define PORT_UINT_CAP_FST_VECT GENMASK_ULL(23, 12) /* First Vector */
172
173 /**
174 * struct dfl_fpga_port_ops - port ops
175 *
176 * @name: name of this port ops, to match with port platform device.
177 * @owner: pointer to the module which owns this port ops.
178 * @node: node to link port ops to global list.
179 * @get_id: get port id from hardware.
180 * @enable_set: enable/disable the port.
181 */
182 struct dfl_fpga_port_ops {
183 const char *name;
184 struct module *owner;
185 struct list_head node;
186 int (*get_id)(struct platform_device *pdev);
187 int (*enable_set)(struct platform_device *pdev, bool enable);
188 };
189
190 void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops);
191 void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops);
192 struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev);
193 void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops);
194 int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id);
195
196 /**
197 * struct dfl_feature_id - dfl private feature id
198 *
199 * @id: unique dfl private feature id.
200 */
201 struct dfl_feature_id {
202 u16 id;
203 };
204
205 /**
206 * struct dfl_feature_driver - dfl private feature driver
207 *
208 * @id_table: id_table for dfl private features supported by this driver.
209 * @ops: ops of this dfl private feature driver.
210 */
211 struct dfl_feature_driver {
212 const struct dfl_feature_id *id_table;
213 const struct dfl_feature_ops *ops;
214 };
215
216 /**
217 * struct dfl_feature_irq_ctx - dfl private feature interrupt context
218 *
219 * @irq: Linux IRQ number of this interrupt.
220 * @trigger: eventfd context to signal when interrupt happens.
221 * @name: irq name needed when requesting irq.
222 */
223 struct dfl_feature_irq_ctx {
224 int irq;
225 struct eventfd_ctx *trigger;
226 char *name;
227 };
228
229 /**
230 * struct dfl_feature - sub feature of the feature devices
231 *
232 * @dev: ptr to pdev of the feature device which has the sub feature.
233 * @id: sub feature id.
234 * @resource_index: each sub feature has one mmio resource for its registers.
235 * this index is used to find its mmio resource from the
236 * feature dev (platform device)'s resources.
237 * @ioaddr: mapped mmio resource address.
238 * @irq_ctx: interrupt context list.
239 * @nr_irqs: number of interrupt contexts.
240 * @ops: ops of this sub feature.
241 * @ddev: ptr to the dfl device of this sub feature.
242 * @priv: priv data of this feature.
243 */
244 struct dfl_feature {
245 struct platform_device *dev;
246 u16 id;
247 u8 revision;
248 int resource_index;
249 void __iomem *ioaddr;
250 struct dfl_feature_irq_ctx *irq_ctx;
251 unsigned int nr_irqs;
252 const struct dfl_feature_ops *ops;
253 struct dfl_device *ddev;
254 void *priv;
255 };
256
257 #define FEATURE_DEV_ID_UNUSED (-1)
258
259 /**
260 * struct dfl_feature_platform_data - platform data for feature devices
261 *
262 * @node: node to link feature devs to container device's port_dev_list.
263 * @lock: mutex to protect platform data.
264 * @cdev: cdev of feature dev.
265 * @dev: ptr to platform device linked with this platform data.
266 * @dfl_cdev: ptr to container device.
267 * @id: id used for this feature device.
268 * @disable_count: count for port disable.
269 * @excl_open: set on feature device exclusive open.
270 * @open_count: count for feature device open.
271 * @num: number for sub features.
272 * @private: ptr to feature dev private data.
273 * @features: sub features of this feature dev.
274 */
275 struct dfl_feature_platform_data {
276 struct list_head node;
277 struct mutex lock;
278 struct cdev cdev;
279 struct platform_device *dev;
280 struct dfl_fpga_cdev *dfl_cdev;
281 int id;
282 unsigned int disable_count;
283 bool excl_open;
284 int open_count;
285 void *private;
286 int num;
287 struct dfl_feature features[];
288 };
289
290 static inline
dfl_feature_dev_use_begin(struct dfl_feature_platform_data * pdata,bool excl)291 int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata,
292 bool excl)
293 {
294 if (pdata->excl_open)
295 return -EBUSY;
296
297 if (excl) {
298 if (pdata->open_count)
299 return -EBUSY;
300
301 pdata->excl_open = true;
302 }
303 pdata->open_count++;
304
305 return 0;
306 }
307
308 static inline
dfl_feature_dev_use_end(struct dfl_feature_platform_data * pdata)309 void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata)
310 {
311 pdata->excl_open = false;
312
313 if (WARN_ON(pdata->open_count <= 0))
314 return;
315
316 pdata->open_count--;
317 }
318
319 static inline
dfl_feature_dev_use_count(struct dfl_feature_platform_data * pdata)320 int dfl_feature_dev_use_count(struct dfl_feature_platform_data *pdata)
321 {
322 return pdata->open_count;
323 }
324
325 static inline
dfl_fpga_pdata_set_private(struct dfl_feature_platform_data * pdata,void * private)326 void dfl_fpga_pdata_set_private(struct dfl_feature_platform_data *pdata,
327 void *private)
328 {
329 pdata->private = private;
330 }
331
332 static inline
dfl_fpga_pdata_get_private(struct dfl_feature_platform_data * pdata)333 void *dfl_fpga_pdata_get_private(struct dfl_feature_platform_data *pdata)
334 {
335 return pdata->private;
336 }
337
338 struct dfl_feature_ops {
339 int (*init)(struct platform_device *pdev, struct dfl_feature *feature);
340 void (*uinit)(struct platform_device *pdev,
341 struct dfl_feature *feature);
342 long (*ioctl)(struct platform_device *pdev, struct dfl_feature *feature,
343 unsigned int cmd, unsigned long arg);
344 };
345
346 #define DFL_FPGA_FEATURE_DEV_FME "dfl-fme"
347 #define DFL_FPGA_FEATURE_DEV_PORT "dfl-port"
348
349 void dfl_fpga_dev_feature_uinit(struct platform_device *pdev);
350 int dfl_fpga_dev_feature_init(struct platform_device *pdev,
351 struct dfl_feature_driver *feature_drvs);
352
353 int dfl_fpga_dev_ops_register(struct platform_device *pdev,
354 const struct file_operations *fops,
355 struct module *owner);
356 void dfl_fpga_dev_ops_unregister(struct platform_device *pdev);
357
358 static inline
dfl_fpga_inode_to_feature_dev(struct inode * inode)359 struct platform_device *dfl_fpga_inode_to_feature_dev(struct inode *inode)
360 {
361 struct dfl_feature_platform_data *pdata;
362
363 pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data,
364 cdev);
365 return pdata->dev;
366 }
367
368 #define dfl_fpga_dev_for_each_feature(pdata, feature) \
369 for ((feature) = (pdata)->features; \
370 (feature) < (pdata)->features + (pdata)->num; (feature)++)
371
372 static inline
dfl_get_feature_by_id(struct device * dev,u16 id)373 struct dfl_feature *dfl_get_feature_by_id(struct device *dev, u16 id)
374 {
375 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
376 struct dfl_feature *feature;
377
378 dfl_fpga_dev_for_each_feature(pdata, feature)
379 if (feature->id == id)
380 return feature;
381
382 return NULL;
383 }
384
385 static inline
dfl_get_feature_ioaddr_by_id(struct device * dev,u16 id)386 void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u16 id)
387 {
388 struct dfl_feature *feature = dfl_get_feature_by_id(dev, id);
389
390 if (feature && feature->ioaddr)
391 return feature->ioaddr;
392
393 WARN_ON(1);
394 return NULL;
395 }
396
is_dfl_feature_present(struct device * dev,u16 id)397 static inline bool is_dfl_feature_present(struct device *dev, u16 id)
398 {
399 return !!dfl_get_feature_ioaddr_by_id(dev, id);
400 }
401
402 static inline
dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data * pdata)403 struct device *dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data *pdata)
404 {
405 return pdata->dev->dev.parent->parent;
406 }
407
dfl_feature_is_fme(void __iomem * base)408 static inline bool dfl_feature_is_fme(void __iomem *base)
409 {
410 u64 v = readq(base + DFH);
411
412 return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
413 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);
414 }
415
dfl_feature_is_port(void __iomem * base)416 static inline bool dfl_feature_is_port(void __iomem *base)
417 {
418 u64 v = readq(base + DFH);
419
420 return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
421 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
422 }
423
dfl_feature_revision(void __iomem * base)424 static inline u8 dfl_feature_revision(void __iomem *base)
425 {
426 return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH));
427 }
428
429 /**
430 * struct dfl_fpga_enum_info - DFL FPGA enumeration information
431 *
432 * @dev: parent device.
433 * @dfls: list of device feature lists.
434 * @nr_irqs: number of irqs for all feature devices.
435 * @irq_table: Linux IRQ numbers for all irqs, indexed by hw irq numbers.
436 */
437 struct dfl_fpga_enum_info {
438 struct device *dev;
439 struct list_head dfls;
440 unsigned int nr_irqs;
441 int *irq_table;
442 };
443
444 /**
445 * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info
446 *
447 * @start: base address of this device feature list.
448 * @len: size of this device feature list.
449 * @node: node in list of device feature lists.
450 */
451 struct dfl_fpga_enum_dfl {
452 resource_size_t start;
453 resource_size_t len;
454 struct list_head node;
455 };
456
457 struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev);
458 int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
459 resource_size_t start, resource_size_t len);
460 int dfl_fpga_enum_info_add_irq(struct dfl_fpga_enum_info *info,
461 unsigned int nr_irqs, int *irq_table);
462 void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);
463
464 /**
465 * struct dfl_fpga_cdev - container device of DFL based FPGA
466 *
467 * @parent: parent device of this container device.
468 * @region: base fpga region.
469 * @fme_dev: FME feature device under this container device.
470 * @lock: mutex lock to protect the port device list.
471 * @port_dev_list: list of all port feature devices under this container device.
472 * @released_port_num: released port number under this container device.
473 */
474 struct dfl_fpga_cdev {
475 struct device *parent;
476 struct fpga_region *region;
477 struct device *fme_dev;
478 struct mutex lock;
479 struct list_head port_dev_list;
480 int released_port_num;
481 };
482
483 struct dfl_fpga_cdev *
484 dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info);
485 void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev);
486
487 /*
488 * need to drop the device reference with put_device() after use port platform
489 * device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port
490 * functions.
491 */
492 struct platform_device *
493 __dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
494 int (*match)(struct platform_device *, void *));
495
496 static inline struct platform_device *
dfl_fpga_cdev_find_port(struct dfl_fpga_cdev * cdev,void * data,int (* match)(struct platform_device *,void *))497 dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
498 int (*match)(struct platform_device *, void *))
499 {
500 struct platform_device *pdev;
501
502 mutex_lock(&cdev->lock);
503 pdev = __dfl_fpga_cdev_find_port(cdev, data, match);
504 mutex_unlock(&cdev->lock);
505
506 return pdev;
507 }
508
509 int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id);
510 int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id);
511 void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev);
512 int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vf);
513 int dfl_fpga_set_irq_triggers(struct dfl_feature *feature, unsigned int start,
514 unsigned int count, int32_t *fds);
515 long dfl_feature_ioctl_get_num_irqs(struct platform_device *pdev,
516 struct dfl_feature *feature,
517 unsigned long arg);
518 long dfl_feature_ioctl_set_irq(struct platform_device *pdev,
519 struct dfl_feature *feature,
520 unsigned long arg);
521
522 #endif /* __FPGA_DFL_H */
523