1 #ifndef A6XX_XML
2 #define A6XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22)
12 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32)
13 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24)
14 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10)
15 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33)
16 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10)
17 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21)
18 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21)
19 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33)
20 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56)
21 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22)
22 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56)
23 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56)
24
25 Copyright (C) 2013-2022 by the following authors:
26 - Rob Clark <robdclark@gmail.com> (robclark)
27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
29 Permission is hereby granted, free of charge, to any person obtaining
30 a copy of this software and associated documentation files (the
31 "Software"), to deal in the Software without restriction, including
32 without limitation the rights to use, copy, modify, merge, publish,
33 distribute, sublicense, and/or sell copies of the Software, and to
34 permit persons to whom the Software is furnished to do so, subject to
35 the following conditions:
36
37 The above copyright notice and this permission notice (including the
38 next paragraph) shall be included in all copies or substantial
39 portions of the Software.
40
41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50
51 enum a6xx_tile_mode {
52 TILE6_LINEAR = 0,
53 TILE6_2 = 2,
54 TILE6_3 = 3,
55 };
56
57 enum a6xx_format {
58 FMT6_A8_UNORM = 2,
59 FMT6_8_UNORM = 3,
60 FMT6_8_SNORM = 4,
61 FMT6_8_UINT = 5,
62 FMT6_8_SINT = 6,
63 FMT6_4_4_4_4_UNORM = 8,
64 FMT6_5_5_5_1_UNORM = 10,
65 FMT6_1_5_5_5_UNORM = 12,
66 FMT6_5_6_5_UNORM = 14,
67 FMT6_8_8_UNORM = 15,
68 FMT6_8_8_SNORM = 16,
69 FMT6_8_8_UINT = 17,
70 FMT6_8_8_SINT = 18,
71 FMT6_L8_A8_UNORM = 19,
72 FMT6_16_UNORM = 21,
73 FMT6_16_SNORM = 22,
74 FMT6_16_FLOAT = 23,
75 FMT6_16_UINT = 24,
76 FMT6_16_SINT = 25,
77 FMT6_8_8_8_UNORM = 33,
78 FMT6_8_8_8_SNORM = 34,
79 FMT6_8_8_8_UINT = 35,
80 FMT6_8_8_8_SINT = 36,
81 FMT6_8_8_8_8_UNORM = 48,
82 FMT6_8_8_8_X8_UNORM = 49,
83 FMT6_8_8_8_8_SNORM = 50,
84 FMT6_8_8_8_8_UINT = 51,
85 FMT6_8_8_8_8_SINT = 52,
86 FMT6_9_9_9_E5_FLOAT = 53,
87 FMT6_10_10_10_2_UNORM = 54,
88 FMT6_10_10_10_2_UNORM_DEST = 55,
89 FMT6_10_10_10_2_SNORM = 57,
90 FMT6_10_10_10_2_UINT = 58,
91 FMT6_10_10_10_2_SINT = 59,
92 FMT6_11_11_10_FLOAT = 66,
93 FMT6_16_16_UNORM = 67,
94 FMT6_16_16_SNORM = 68,
95 FMT6_16_16_FLOAT = 69,
96 FMT6_16_16_UINT = 70,
97 FMT6_16_16_SINT = 71,
98 FMT6_32_UNORM = 72,
99 FMT6_32_SNORM = 73,
100 FMT6_32_FLOAT = 74,
101 FMT6_32_UINT = 75,
102 FMT6_32_SINT = 76,
103 FMT6_32_FIXED = 77,
104 FMT6_16_16_16_UNORM = 88,
105 FMT6_16_16_16_SNORM = 89,
106 FMT6_16_16_16_FLOAT = 90,
107 FMT6_16_16_16_UINT = 91,
108 FMT6_16_16_16_SINT = 92,
109 FMT6_16_16_16_16_UNORM = 96,
110 FMT6_16_16_16_16_SNORM = 97,
111 FMT6_16_16_16_16_FLOAT = 98,
112 FMT6_16_16_16_16_UINT = 99,
113 FMT6_16_16_16_16_SINT = 100,
114 FMT6_32_32_UNORM = 101,
115 FMT6_32_32_SNORM = 102,
116 FMT6_32_32_FLOAT = 103,
117 FMT6_32_32_UINT = 104,
118 FMT6_32_32_SINT = 105,
119 FMT6_32_32_FIXED = 106,
120 FMT6_32_32_32_UNORM = 112,
121 FMT6_32_32_32_SNORM = 113,
122 FMT6_32_32_32_UINT = 114,
123 FMT6_32_32_32_SINT = 115,
124 FMT6_32_32_32_FLOAT = 116,
125 FMT6_32_32_32_FIXED = 117,
126 FMT6_32_32_32_32_UNORM = 128,
127 FMT6_32_32_32_32_SNORM = 129,
128 FMT6_32_32_32_32_FLOAT = 130,
129 FMT6_32_32_32_32_UINT = 131,
130 FMT6_32_32_32_32_SINT = 132,
131 FMT6_32_32_32_32_FIXED = 133,
132 FMT6_G8R8B8R8_422_UNORM = 140,
133 FMT6_R8G8R8B8_422_UNORM = 141,
134 FMT6_R8_G8B8_2PLANE_420_UNORM = 142,
135 FMT6_NV21 = 143,
136 FMT6_R8_G8_B8_3PLANE_420_UNORM = 144,
137 FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145,
138 FMT6_NV12_Y = 148,
139 FMT6_NV12_UV = 149,
140 FMT6_NV12_VU = 150,
141 FMT6_NV12_4R = 151,
142 FMT6_NV12_4R_Y = 152,
143 FMT6_NV12_4R_UV = 153,
144 FMT6_P010 = 154,
145 FMT6_P010_Y = 155,
146 FMT6_P010_UV = 156,
147 FMT6_TP10 = 157,
148 FMT6_TP10_Y = 158,
149 FMT6_TP10_UV = 159,
150 FMT6_Z24_UNORM_S8_UINT = 160,
151 FMT6_ETC2_RG11_UNORM = 171,
152 FMT6_ETC2_RG11_SNORM = 172,
153 FMT6_ETC2_R11_UNORM = 173,
154 FMT6_ETC2_R11_SNORM = 174,
155 FMT6_ETC1 = 175,
156 FMT6_ETC2_RGB8 = 176,
157 FMT6_ETC2_RGBA8 = 177,
158 FMT6_ETC2_RGB8A1 = 178,
159 FMT6_DXT1 = 179,
160 FMT6_DXT3 = 180,
161 FMT6_DXT5 = 181,
162 FMT6_RGTC1_UNORM = 183,
163 FMT6_RGTC1_SNORM = 184,
164 FMT6_RGTC2_UNORM = 187,
165 FMT6_RGTC2_SNORM = 188,
166 FMT6_BPTC_UFLOAT = 190,
167 FMT6_BPTC_FLOAT = 191,
168 FMT6_BPTC = 192,
169 FMT6_ASTC_4x4 = 193,
170 FMT6_ASTC_5x4 = 194,
171 FMT6_ASTC_5x5 = 195,
172 FMT6_ASTC_6x5 = 196,
173 FMT6_ASTC_6x6 = 197,
174 FMT6_ASTC_8x5 = 198,
175 FMT6_ASTC_8x6 = 199,
176 FMT6_ASTC_8x8 = 200,
177 FMT6_ASTC_10x5 = 201,
178 FMT6_ASTC_10x6 = 202,
179 FMT6_ASTC_10x8 = 203,
180 FMT6_ASTC_10x10 = 204,
181 FMT6_ASTC_12x10 = 205,
182 FMT6_ASTC_12x12 = 206,
183 FMT6_Z24_UINT_S8_UINT = 234,
184 FMT6_NONE = 255,
185 };
186
187 enum a6xx_polygon_mode {
188 POLYMODE6_POINTS = 1,
189 POLYMODE6_LINES = 2,
190 POLYMODE6_TRIANGLES = 3,
191 };
192
193 enum a6xx_depth_format {
194 DEPTH6_NONE = 0,
195 DEPTH6_16 = 1,
196 DEPTH6_24_8 = 2,
197 DEPTH6_32 = 4,
198 };
199
200 enum a6xx_shader_id {
201 A6XX_TP0_TMO_DATA = 9,
202 A6XX_TP0_SMO_DATA = 10,
203 A6XX_TP0_MIPMAP_BASE_DATA = 11,
204 A6XX_TP1_TMO_DATA = 25,
205 A6XX_TP1_SMO_DATA = 26,
206 A6XX_TP1_MIPMAP_BASE_DATA = 27,
207 A6XX_SP_INST_DATA = 41,
208 A6XX_SP_LB_0_DATA = 42,
209 A6XX_SP_LB_1_DATA = 43,
210 A6XX_SP_LB_2_DATA = 44,
211 A6XX_SP_LB_3_DATA = 45,
212 A6XX_SP_LB_4_DATA = 46,
213 A6XX_SP_LB_5_DATA = 47,
214 A6XX_SP_CB_BINDLESS_DATA = 48,
215 A6XX_SP_CB_LEGACY_DATA = 49,
216 A6XX_SP_UAV_DATA = 50,
217 A6XX_SP_INST_TAG = 51,
218 A6XX_SP_CB_BINDLESS_TAG = 52,
219 A6XX_SP_TMO_UMO_TAG = 53,
220 A6XX_SP_SMO_TAG = 54,
221 A6XX_SP_STATE_DATA = 55,
222 A6XX_HLSQ_CHUNK_CVS_RAM = 73,
223 A6XX_HLSQ_CHUNK_CPS_RAM = 74,
224 A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75,
225 A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76,
226 A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77,
227 A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78,
228 A6XX_HLSQ_CVS_MISC_RAM = 80,
229 A6XX_HLSQ_CPS_MISC_RAM = 81,
230 A6XX_HLSQ_INST_RAM = 82,
231 A6XX_HLSQ_GFX_CVS_CONST_RAM = 83,
232 A6XX_HLSQ_GFX_CPS_CONST_RAM = 84,
233 A6XX_HLSQ_CVS_MISC_RAM_TAG = 85,
234 A6XX_HLSQ_CPS_MISC_RAM_TAG = 86,
235 A6XX_HLSQ_INST_RAM_TAG = 87,
236 A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88,
237 A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89,
238 A6XX_HLSQ_PWR_REST_RAM = 90,
239 A6XX_HLSQ_PWR_REST_TAG = 91,
240 A6XX_HLSQ_DATAPATH_META = 96,
241 A6XX_HLSQ_FRONTEND_META = 97,
242 A6XX_HLSQ_INDIRECT_META = 98,
243 A6XX_HLSQ_BACKEND_META = 99,
244 };
245
246 enum a6xx_debugbus_id {
247 A6XX_DBGBUS_CP = 1,
248 A6XX_DBGBUS_RBBM = 2,
249 A6XX_DBGBUS_VBIF = 3,
250 A6XX_DBGBUS_HLSQ = 4,
251 A6XX_DBGBUS_UCHE = 5,
252 A6XX_DBGBUS_DPM = 6,
253 A6XX_DBGBUS_TESS = 7,
254 A6XX_DBGBUS_PC = 8,
255 A6XX_DBGBUS_VFDP = 9,
256 A6XX_DBGBUS_VPC = 10,
257 A6XX_DBGBUS_TSE = 11,
258 A6XX_DBGBUS_RAS = 12,
259 A6XX_DBGBUS_VSC = 13,
260 A6XX_DBGBUS_COM = 14,
261 A6XX_DBGBUS_LRZ = 16,
262 A6XX_DBGBUS_A2D = 17,
263 A6XX_DBGBUS_CCUFCHE = 18,
264 A6XX_DBGBUS_GMU_CX = 19,
265 A6XX_DBGBUS_RBP = 20,
266 A6XX_DBGBUS_DCS = 21,
267 A6XX_DBGBUS_DBGC = 22,
268 A6XX_DBGBUS_CX = 23,
269 A6XX_DBGBUS_GMU_GX = 24,
270 A6XX_DBGBUS_TPFCHE = 25,
271 A6XX_DBGBUS_GBIF_GX = 26,
272 A6XX_DBGBUS_GPC = 29,
273 A6XX_DBGBUS_LARC = 30,
274 A6XX_DBGBUS_HLSQ_SPTP = 31,
275 A6XX_DBGBUS_RB_0 = 32,
276 A6XX_DBGBUS_RB_1 = 33,
277 A6XX_DBGBUS_UCHE_WRAPPER = 36,
278 A6XX_DBGBUS_CCU_0 = 40,
279 A6XX_DBGBUS_CCU_1 = 41,
280 A6XX_DBGBUS_VFD_0 = 56,
281 A6XX_DBGBUS_VFD_1 = 57,
282 A6XX_DBGBUS_VFD_2 = 58,
283 A6XX_DBGBUS_VFD_3 = 59,
284 A6XX_DBGBUS_SP_0 = 64,
285 A6XX_DBGBUS_SP_1 = 65,
286 A6XX_DBGBUS_TPL1_0 = 72,
287 A6XX_DBGBUS_TPL1_1 = 73,
288 A6XX_DBGBUS_TPL1_2 = 74,
289 A6XX_DBGBUS_TPL1_3 = 75,
290 };
291
292 enum a6xx_cp_perfcounter_select {
293 PERF_CP_ALWAYS_COUNT = 0,
294 PERF_CP_BUSY_GFX_CORE_IDLE = 1,
295 PERF_CP_BUSY_CYCLES = 2,
296 PERF_CP_NUM_PREEMPTIONS = 3,
297 PERF_CP_PREEMPTION_REACTION_DELAY = 4,
298 PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5,
299 PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6,
300 PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7,
301 PERF_CP_PREDICATED_DRAWS_KILLED = 8,
302 PERF_CP_MODE_SWITCH = 9,
303 PERF_CP_ZPASS_DONE = 10,
304 PERF_CP_CONTEXT_DONE = 11,
305 PERF_CP_CACHE_FLUSH = 12,
306 PERF_CP_LONG_PREEMPTIONS = 13,
307 PERF_CP_SQE_I_CACHE_STARVE = 14,
308 PERF_CP_SQE_IDLE = 15,
309 PERF_CP_SQE_PM4_STARVE_RB_IB = 16,
310 PERF_CP_SQE_PM4_STARVE_SDS = 17,
311 PERF_CP_SQE_MRB_STARVE = 18,
312 PERF_CP_SQE_RRB_STARVE = 19,
313 PERF_CP_SQE_VSD_STARVE = 20,
314 PERF_CP_VSD_DECODE_STARVE = 21,
315 PERF_CP_SQE_PIPE_OUT_STALL = 22,
316 PERF_CP_SQE_SYNC_STALL = 23,
317 PERF_CP_SQE_PM4_WFI_STALL = 24,
318 PERF_CP_SQE_SYS_WFI_STALL = 25,
319 PERF_CP_SQE_T4_EXEC = 26,
320 PERF_CP_SQE_LOAD_STATE_EXEC = 27,
321 PERF_CP_SQE_SAVE_SDS_STATE = 28,
322 PERF_CP_SQE_DRAW_EXEC = 29,
323 PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30,
324 PERF_CP_SQE_EXEC_PROFILED = 31,
325 PERF_CP_MEMORY_POOL_EMPTY = 32,
326 PERF_CP_MEMORY_POOL_SYNC_STALL = 33,
327 PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34,
328 PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35,
329 PERF_CP_AHB_STALL_SQE_GMU = 36,
330 PERF_CP_AHB_STALL_SQE_WR_OTHER = 37,
331 PERF_CP_AHB_STALL_SQE_RD_OTHER = 38,
332 PERF_CP_CLUSTER0_EMPTY = 39,
333 PERF_CP_CLUSTER1_EMPTY = 40,
334 PERF_CP_CLUSTER2_EMPTY = 41,
335 PERF_CP_CLUSTER3_EMPTY = 42,
336 PERF_CP_CLUSTER4_EMPTY = 43,
337 PERF_CP_CLUSTER5_EMPTY = 44,
338 PERF_CP_PM4_DATA = 45,
339 PERF_CP_PM4_HEADERS = 46,
340 PERF_CP_VBIF_READ_BEATS = 47,
341 PERF_CP_VBIF_WRITE_BEATS = 48,
342 PERF_CP_SQE_INSTR_COUNTER = 49,
343 };
344
345 enum a6xx_rbbm_perfcounter_select {
346 PERF_RBBM_ALWAYS_COUNT = 0,
347 PERF_RBBM_ALWAYS_ON = 1,
348 PERF_RBBM_TSE_BUSY = 2,
349 PERF_RBBM_RAS_BUSY = 3,
350 PERF_RBBM_PC_DCALL_BUSY = 4,
351 PERF_RBBM_PC_VSD_BUSY = 5,
352 PERF_RBBM_STATUS_MASKED = 6,
353 PERF_RBBM_COM_BUSY = 7,
354 PERF_RBBM_DCOM_BUSY = 8,
355 PERF_RBBM_VBIF_BUSY = 9,
356 PERF_RBBM_VSC_BUSY = 10,
357 PERF_RBBM_TESS_BUSY = 11,
358 PERF_RBBM_UCHE_BUSY = 12,
359 PERF_RBBM_HLSQ_BUSY = 13,
360 };
361
362 enum a6xx_pc_perfcounter_select {
363 PERF_PC_BUSY_CYCLES = 0,
364 PERF_PC_WORKING_CYCLES = 1,
365 PERF_PC_STALL_CYCLES_VFD = 2,
366 PERF_PC_STALL_CYCLES_TSE = 3,
367 PERF_PC_STALL_CYCLES_VPC = 4,
368 PERF_PC_STALL_CYCLES_UCHE = 5,
369 PERF_PC_STALL_CYCLES_TESS = 6,
370 PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
371 PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
372 PERF_PC_PASS1_TF_STALL_CYCLES = 9,
373 PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
374 PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
375 PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
376 PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
377 PERF_PC_STARVE_CYCLES_DI = 14,
378 PERF_PC_VIS_STREAMS_LOADED = 15,
379 PERF_PC_INSTANCES = 16,
380 PERF_PC_VPC_PRIMITIVES = 17,
381 PERF_PC_DEAD_PRIM = 18,
382 PERF_PC_LIVE_PRIM = 19,
383 PERF_PC_VERTEX_HITS = 20,
384 PERF_PC_IA_VERTICES = 21,
385 PERF_PC_IA_PRIMITIVES = 22,
386 PERF_PC_GS_PRIMITIVES = 23,
387 PERF_PC_HS_INVOCATIONS = 24,
388 PERF_PC_DS_INVOCATIONS = 25,
389 PERF_PC_VS_INVOCATIONS = 26,
390 PERF_PC_GS_INVOCATIONS = 27,
391 PERF_PC_DS_PRIMITIVES = 28,
392 PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
393 PERF_PC_3D_DRAWCALLS = 30,
394 PERF_PC_2D_DRAWCALLS = 31,
395 PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
396 PERF_TESS_BUSY_CYCLES = 33,
397 PERF_TESS_WORKING_CYCLES = 34,
398 PERF_TESS_STALL_CYCLES_PC = 35,
399 PERF_TESS_STARVE_CYCLES_PC = 36,
400 PERF_PC_TSE_TRANSACTION = 37,
401 PERF_PC_TSE_VERTEX = 38,
402 PERF_PC_TESS_PC_UV_TRANS = 39,
403 PERF_PC_TESS_PC_UV_PATCHES = 40,
404 PERF_PC_TESS_FACTOR_TRANS = 41,
405 };
406
407 enum a6xx_vfd_perfcounter_select {
408 PERF_VFD_BUSY_CYCLES = 0,
409 PERF_VFD_STALL_CYCLES_UCHE = 1,
410 PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
411 PERF_VFD_STALL_CYCLES_SP_INFO = 3,
412 PERF_VFD_STALL_CYCLES_SP_ATTR = 4,
413 PERF_VFD_STARVE_CYCLES_UCHE = 5,
414 PERF_VFD_RBUFFER_FULL = 6,
415 PERF_VFD_ATTR_INFO_FIFO_FULL = 7,
416 PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8,
417 PERF_VFD_NUM_ATTRIBUTES = 9,
418 PERF_VFD_UPPER_SHADER_FIBERS = 10,
419 PERF_VFD_LOWER_SHADER_FIBERS = 11,
420 PERF_VFD_MODE_0_FIBERS = 12,
421 PERF_VFD_MODE_1_FIBERS = 13,
422 PERF_VFD_MODE_2_FIBERS = 14,
423 PERF_VFD_MODE_3_FIBERS = 15,
424 PERF_VFD_MODE_4_FIBERS = 16,
425 PERF_VFD_TOTAL_VERTICES = 17,
426 PERF_VFDP_STALL_CYCLES_VFD = 18,
427 PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19,
428 PERF_VFDP_STALL_CYCLES_VFD_PROG = 20,
429 PERF_VFDP_STARVE_CYCLES_PC = 21,
430 PERF_VFDP_VS_STAGE_WAVES = 22,
431 };
432
433 enum a6xx_hlsq_perfcounter_select {
434 PERF_HLSQ_BUSY_CYCLES = 0,
435 PERF_HLSQ_STALL_CYCLES_UCHE = 1,
436 PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
437 PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
438 PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
439 PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
440 PERF_HLSQ_FS_STAGE_1X_WAVES = 6,
441 PERF_HLSQ_FS_STAGE_2X_WAVES = 7,
442 PERF_HLSQ_QUADS = 8,
443 PERF_HLSQ_CS_INVOCATIONS = 9,
444 PERF_HLSQ_COMPUTE_DRAWCALLS = 10,
445 PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11,
446 PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12,
447 PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13,
448 PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14,
449 PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15,
450 PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16,
451 PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17,
452 PERF_HLSQ_STALL_CYCLES_VPC = 18,
453 PERF_HLSQ_PIXELS = 19,
454 PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20,
455 };
456
457 enum a6xx_vpc_perfcounter_select {
458 PERF_VPC_BUSY_CYCLES = 0,
459 PERF_VPC_WORKING_CYCLES = 1,
460 PERF_VPC_STALL_CYCLES_UCHE = 2,
461 PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
462 PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
463 PERF_VPC_STALL_CYCLES_PC = 5,
464 PERF_VPC_STALL_CYCLES_SP_LM = 6,
465 PERF_VPC_STARVE_CYCLES_SP = 7,
466 PERF_VPC_STARVE_CYCLES_LRZ = 8,
467 PERF_VPC_PC_PRIMITIVES = 9,
468 PERF_VPC_SP_COMPONENTS = 10,
469 PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11,
470 PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12,
471 PERF_VPC_RB_VISIBLE_PRIMITIVES = 13,
472 PERF_VPC_LM_TRANSACTION = 14,
473 PERF_VPC_STREAMOUT_TRANSACTION = 15,
474 PERF_VPC_VS_BUSY_CYCLES = 16,
475 PERF_VPC_PS_BUSY_CYCLES = 17,
476 PERF_VPC_VS_WORKING_CYCLES = 18,
477 PERF_VPC_PS_WORKING_CYCLES = 19,
478 PERF_VPC_STARVE_CYCLES_RB = 20,
479 PERF_VPC_NUM_VPCRAM_READ_POS = 21,
480 PERF_VPC_WIT_FULL_CYCLES = 22,
481 PERF_VPC_VPCRAM_FULL_CYCLES = 23,
482 PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24,
483 PERF_VPC_NUM_VPCRAM_WRITE = 25,
484 PERF_VPC_NUM_VPCRAM_READ_SO = 26,
485 PERF_VPC_NUM_ATTR_REQ_LM = 27,
486 };
487
488 enum a6xx_tse_perfcounter_select {
489 PERF_TSE_BUSY_CYCLES = 0,
490 PERF_TSE_CLIPPING_CYCLES = 1,
491 PERF_TSE_STALL_CYCLES_RAS = 2,
492 PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
493 PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
494 PERF_TSE_STARVE_CYCLES_PC = 5,
495 PERF_TSE_INPUT_PRIM = 6,
496 PERF_TSE_INPUT_NULL_PRIM = 7,
497 PERF_TSE_TRIVAL_REJ_PRIM = 8,
498 PERF_TSE_CLIPPED_PRIM = 9,
499 PERF_TSE_ZERO_AREA_PRIM = 10,
500 PERF_TSE_FACENESS_CULLED_PRIM = 11,
501 PERF_TSE_ZERO_PIXEL_PRIM = 12,
502 PERF_TSE_OUTPUT_NULL_PRIM = 13,
503 PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
504 PERF_TSE_CINVOCATION = 15,
505 PERF_TSE_CPRIMITIVES = 16,
506 PERF_TSE_2D_INPUT_PRIM = 17,
507 PERF_TSE_2D_ALIVE_CYCLES = 18,
508 PERF_TSE_CLIP_PLANES = 19,
509 };
510
511 enum a6xx_ras_perfcounter_select {
512 PERF_RAS_BUSY_CYCLES = 0,
513 PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
514 PERF_RAS_STALL_CYCLES_LRZ = 2,
515 PERF_RAS_STARVE_CYCLES_TSE = 3,
516 PERF_RAS_SUPER_TILES = 4,
517 PERF_RAS_8X4_TILES = 5,
518 PERF_RAS_MASKGEN_ACTIVE = 6,
519 PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
520 PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
521 PERF_RAS_PRIM_KILLED_INVISILBE = 9,
522 PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10,
523 PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11,
524 PERF_RAS_BLOCKS = 12,
525 };
526
527 enum a6xx_uche_perfcounter_select {
528 PERF_UCHE_BUSY_CYCLES = 0,
529 PERF_UCHE_STALL_CYCLES_ARBITER = 1,
530 PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
531 PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
532 PERF_UCHE_VBIF_READ_BEATS_TP = 4,
533 PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
534 PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
535 PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
536 PERF_UCHE_VBIF_READ_BEATS_SP = 8,
537 PERF_UCHE_READ_REQUESTS_TP = 9,
538 PERF_UCHE_READ_REQUESTS_VFD = 10,
539 PERF_UCHE_READ_REQUESTS_HLSQ = 11,
540 PERF_UCHE_READ_REQUESTS_LRZ = 12,
541 PERF_UCHE_READ_REQUESTS_SP = 13,
542 PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
543 PERF_UCHE_WRITE_REQUESTS_SP = 15,
544 PERF_UCHE_WRITE_REQUESTS_VPC = 16,
545 PERF_UCHE_WRITE_REQUESTS_VSC = 17,
546 PERF_UCHE_EVICTS = 18,
547 PERF_UCHE_BANK_REQ0 = 19,
548 PERF_UCHE_BANK_REQ1 = 20,
549 PERF_UCHE_BANK_REQ2 = 21,
550 PERF_UCHE_BANK_REQ3 = 22,
551 PERF_UCHE_BANK_REQ4 = 23,
552 PERF_UCHE_BANK_REQ5 = 24,
553 PERF_UCHE_BANK_REQ6 = 25,
554 PERF_UCHE_BANK_REQ7 = 26,
555 PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
556 PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
557 PERF_UCHE_GMEM_READ_BEATS = 29,
558 PERF_UCHE_TPH_REF_FULL = 30,
559 PERF_UCHE_TPH_VICTIM_FULL = 31,
560 PERF_UCHE_TPH_EXT_FULL = 32,
561 PERF_UCHE_VBIF_STALL_WRITE_DATA = 33,
562 PERF_UCHE_DCMP_LATENCY_SAMPLES = 34,
563 PERF_UCHE_DCMP_LATENCY_CYCLES = 35,
564 PERF_UCHE_VBIF_READ_BEATS_PC = 36,
565 PERF_UCHE_READ_REQUESTS_PC = 37,
566 PERF_UCHE_RAM_READ_REQ = 38,
567 PERF_UCHE_RAM_WRITE_REQ = 39,
568 };
569
570 enum a6xx_tp_perfcounter_select {
571 PERF_TP_BUSY_CYCLES = 0,
572 PERF_TP_STALL_CYCLES_UCHE = 1,
573 PERF_TP_LATENCY_CYCLES = 2,
574 PERF_TP_LATENCY_TRANS = 3,
575 PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
576 PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
577 PERF_TP_L1_CACHELINE_REQUESTS = 6,
578 PERF_TP_L1_CACHELINE_MISSES = 7,
579 PERF_TP_SP_TP_TRANS = 8,
580 PERF_TP_TP_SP_TRANS = 9,
581 PERF_TP_OUTPUT_PIXELS = 10,
582 PERF_TP_FILTER_WORKLOAD_16BIT = 11,
583 PERF_TP_FILTER_WORKLOAD_32BIT = 12,
584 PERF_TP_QUADS_RECEIVED = 13,
585 PERF_TP_QUADS_OFFSET = 14,
586 PERF_TP_QUADS_SHADOW = 15,
587 PERF_TP_QUADS_ARRAY = 16,
588 PERF_TP_QUADS_GRADIENT = 17,
589 PERF_TP_QUADS_1D = 18,
590 PERF_TP_QUADS_2D = 19,
591 PERF_TP_QUADS_BUFFER = 20,
592 PERF_TP_QUADS_3D = 21,
593 PERF_TP_QUADS_CUBE = 22,
594 PERF_TP_DIVERGENT_QUADS_RECEIVED = 23,
595 PERF_TP_PRT_NON_RESIDENT_EVENTS = 24,
596 PERF_TP_OUTPUT_PIXELS_POINT = 25,
597 PERF_TP_OUTPUT_PIXELS_BILINEAR = 26,
598 PERF_TP_OUTPUT_PIXELS_MIP = 27,
599 PERF_TP_OUTPUT_PIXELS_ANISO = 28,
600 PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29,
601 PERF_TP_FLAG_CACHE_REQUESTS = 30,
602 PERF_TP_FLAG_CACHE_MISSES = 31,
603 PERF_TP_L1_5_L2_REQUESTS = 32,
604 PERF_TP_2D_OUTPUT_PIXELS = 33,
605 PERF_TP_2D_OUTPUT_PIXELS_POINT = 34,
606 PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35,
607 PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36,
608 PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37,
609 PERF_TP_TPA2TPC_TRANS = 38,
610 PERF_TP_L1_MISSES_ASTC_1TILE = 39,
611 PERF_TP_L1_MISSES_ASTC_2TILE = 40,
612 PERF_TP_L1_MISSES_ASTC_4TILE = 41,
613 PERF_TP_L1_5_L2_COMPRESS_REQS = 42,
614 PERF_TP_L1_5_L2_COMPRESS_MISS = 43,
615 PERF_TP_L1_BANK_CONFLICT = 44,
616 PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45,
617 PERF_TP_L1_5_MISS_LATENCY_TRANS = 46,
618 PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47,
619 PERF_TP_FRONTEND_WORKING_CYCLES = 48,
620 PERF_TP_L1_TAG_WORKING_CYCLES = 49,
621 PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50,
622 PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51,
623 PERF_TP_BACKEND_WORKING_CYCLES = 52,
624 PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53,
625 PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54,
626 PERF_TP_STARVE_CYCLES_SP = 55,
627 PERF_TP_STARVE_CYCLES_UCHE = 56,
628 };
629
630 enum a6xx_sp_perfcounter_select {
631 PERF_SP_BUSY_CYCLES = 0,
632 PERF_SP_ALU_WORKING_CYCLES = 1,
633 PERF_SP_EFU_WORKING_CYCLES = 2,
634 PERF_SP_STALL_CYCLES_VPC = 3,
635 PERF_SP_STALL_CYCLES_TP = 4,
636 PERF_SP_STALL_CYCLES_UCHE = 5,
637 PERF_SP_STALL_CYCLES_RB = 6,
638 PERF_SP_NON_EXECUTION_CYCLES = 7,
639 PERF_SP_WAVE_CONTEXTS = 8,
640 PERF_SP_WAVE_CONTEXT_CYCLES = 9,
641 PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
642 PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
643 PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
644 PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
645 PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
646 PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
647 PERF_SP_WAVE_CTRL_CYCLES = 16,
648 PERF_SP_WAVE_LOAD_CYCLES = 17,
649 PERF_SP_WAVE_EMIT_CYCLES = 18,
650 PERF_SP_WAVE_NOP_CYCLES = 19,
651 PERF_SP_WAVE_WAIT_CYCLES = 20,
652 PERF_SP_WAVE_FETCH_CYCLES = 21,
653 PERF_SP_WAVE_IDLE_CYCLES = 22,
654 PERF_SP_WAVE_END_CYCLES = 23,
655 PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
656 PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
657 PERF_SP_WAVE_JOIN_CYCLES = 26,
658 PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
659 PERF_SP_LM_STORE_INSTRUCTIONS = 28,
660 PERF_SP_LM_ATOMICS = 29,
661 PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
662 PERF_SP_GM_STORE_INSTRUCTIONS = 31,
663 PERF_SP_GM_ATOMICS = 32,
664 PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
665 PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34,
666 PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35,
667 PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36,
668 PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37,
669 PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38,
670 PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39,
671 PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40,
672 PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41,
673 PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42,
674 PERF_SP_VS_INSTRUCTIONS = 43,
675 PERF_SP_FS_INSTRUCTIONS = 44,
676 PERF_SP_ADDR_LOCK_COUNT = 45,
677 PERF_SP_UCHE_READ_TRANS = 46,
678 PERF_SP_UCHE_WRITE_TRANS = 47,
679 PERF_SP_EXPORT_VPC_TRANS = 48,
680 PERF_SP_EXPORT_RB_TRANS = 49,
681 PERF_SP_PIXELS_KILLED = 50,
682 PERF_SP_ICL1_REQUESTS = 51,
683 PERF_SP_ICL1_MISSES = 52,
684 PERF_SP_HS_INSTRUCTIONS = 53,
685 PERF_SP_DS_INSTRUCTIONS = 54,
686 PERF_SP_GS_INSTRUCTIONS = 55,
687 PERF_SP_CS_INSTRUCTIONS = 56,
688 PERF_SP_GPR_READ = 57,
689 PERF_SP_GPR_WRITE = 58,
690 PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59,
691 PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60,
692 PERF_SP_LM_BANK_CONFLICTS = 61,
693 PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62,
694 PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63,
695 PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64,
696 PERF_SP_LM_WORKING_CYCLES = 65,
697 PERF_SP_DISPATCHER_WORKING_CYCLES = 66,
698 PERF_SP_SEQUENCER_WORKING_CYCLES = 67,
699 PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68,
700 PERF_SP_STARVE_CYCLES_HLSQ = 69,
701 PERF_SP_NON_EXECUTION_LS_CYCLES = 70,
702 PERF_SP_WORKING_EU = 71,
703 PERF_SP_ANY_EU_WORKING = 72,
704 PERF_SP_WORKING_EU_FS_STAGE = 73,
705 PERF_SP_ANY_EU_WORKING_FS_STAGE = 74,
706 PERF_SP_WORKING_EU_VS_STAGE = 75,
707 PERF_SP_ANY_EU_WORKING_VS_STAGE = 76,
708 PERF_SP_WORKING_EU_CS_STAGE = 77,
709 PERF_SP_ANY_EU_WORKING_CS_STAGE = 78,
710 PERF_SP_GPR_READ_PREFETCH = 79,
711 PERF_SP_GPR_READ_CONFLICT = 80,
712 PERF_SP_GPR_WRITE_CONFLICT = 81,
713 PERF_SP_GM_LOAD_LATENCY_CYCLES = 82,
714 PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83,
715 PERF_SP_EXECUTABLE_WAVES = 84,
716 };
717
718 enum a6xx_rb_perfcounter_select {
719 PERF_RB_BUSY_CYCLES = 0,
720 PERF_RB_STALL_CYCLES_HLSQ = 1,
721 PERF_RB_STALL_CYCLES_FIFO0_FULL = 2,
722 PERF_RB_STALL_CYCLES_FIFO1_FULL = 3,
723 PERF_RB_STALL_CYCLES_FIFO2_FULL = 4,
724 PERF_RB_STARVE_CYCLES_SP = 5,
725 PERF_RB_STARVE_CYCLES_LRZ_TILE = 6,
726 PERF_RB_STARVE_CYCLES_CCU = 7,
727 PERF_RB_STARVE_CYCLES_Z_PLANE = 8,
728 PERF_RB_STARVE_CYCLES_BARY_PLANE = 9,
729 PERF_RB_Z_WORKLOAD = 10,
730 PERF_RB_HLSQ_ACTIVE = 11,
731 PERF_RB_Z_READ = 12,
732 PERF_RB_Z_WRITE = 13,
733 PERF_RB_C_READ = 14,
734 PERF_RB_C_WRITE = 15,
735 PERF_RB_TOTAL_PASS = 16,
736 PERF_RB_Z_PASS = 17,
737 PERF_RB_Z_FAIL = 18,
738 PERF_RB_S_FAIL = 19,
739 PERF_RB_BLENDED_FXP_COMPONENTS = 20,
740 PERF_RB_BLENDED_FP16_COMPONENTS = 21,
741 PERF_RB_PS_INVOCATIONS = 22,
742 PERF_RB_2D_ALIVE_CYCLES = 23,
743 PERF_RB_2D_STALL_CYCLES_A2D = 24,
744 PERF_RB_2D_STARVE_CYCLES_SRC = 25,
745 PERF_RB_2D_STARVE_CYCLES_SP = 26,
746 PERF_RB_2D_STARVE_CYCLES_DST = 27,
747 PERF_RB_2D_VALID_PIXELS = 28,
748 PERF_RB_3D_PIXELS = 29,
749 PERF_RB_BLENDER_WORKING_CYCLES = 30,
750 PERF_RB_ZPROC_WORKING_CYCLES = 31,
751 PERF_RB_CPROC_WORKING_CYCLES = 32,
752 PERF_RB_SAMPLER_WORKING_CYCLES = 33,
753 PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34,
754 PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35,
755 PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36,
756 PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37,
757 PERF_RB_STALL_CYCLES_VPC = 38,
758 PERF_RB_2D_INPUT_TRANS = 39,
759 PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40,
760 PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41,
761 PERF_RB_BLENDED_FP32_COMPONENTS = 42,
762 PERF_RB_COLOR_PIX_TILES = 43,
763 PERF_RB_STALL_CYCLES_CCU = 44,
764 PERF_RB_EARLY_Z_ARB3_GRANT = 45,
765 PERF_RB_LATE_Z_ARB3_GRANT = 46,
766 PERF_RB_EARLY_Z_SKIP_GRANT = 47,
767 };
768
769 enum a6xx_vsc_perfcounter_select {
770 PERF_VSC_BUSY_CYCLES = 0,
771 PERF_VSC_WORKING_CYCLES = 1,
772 PERF_VSC_STALL_CYCLES_UCHE = 2,
773 PERF_VSC_EOT_NUM = 3,
774 PERF_VSC_INPUT_TILES = 4,
775 };
776
777 enum a6xx_ccu_perfcounter_select {
778 PERF_CCU_BUSY_CYCLES = 0,
779 PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
780 PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
781 PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
782 PERF_CCU_DEPTH_BLOCKS = 4,
783 PERF_CCU_COLOR_BLOCKS = 5,
784 PERF_CCU_DEPTH_BLOCK_HIT = 6,
785 PERF_CCU_COLOR_BLOCK_HIT = 7,
786 PERF_CCU_PARTIAL_BLOCK_READ = 8,
787 PERF_CCU_GMEM_READ = 9,
788 PERF_CCU_GMEM_WRITE = 10,
789 PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
790 PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
791 PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
792 PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
793 PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
794 PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16,
795 PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17,
796 PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18,
797 PERF_CCU_COLOR_READ_FLAG0_COUNT = 19,
798 PERF_CCU_COLOR_READ_FLAG1_COUNT = 20,
799 PERF_CCU_COLOR_READ_FLAG2_COUNT = 21,
800 PERF_CCU_COLOR_READ_FLAG3_COUNT = 22,
801 PERF_CCU_COLOR_READ_FLAG4_COUNT = 23,
802 PERF_CCU_COLOR_READ_FLAG5_COUNT = 24,
803 PERF_CCU_COLOR_READ_FLAG6_COUNT = 25,
804 PERF_CCU_COLOR_READ_FLAG8_COUNT = 26,
805 PERF_CCU_2D_RD_REQ = 27,
806 PERF_CCU_2D_WR_REQ = 28,
807 };
808
809 enum a6xx_lrz_perfcounter_select {
810 PERF_LRZ_BUSY_CYCLES = 0,
811 PERF_LRZ_STARVE_CYCLES_RAS = 1,
812 PERF_LRZ_STALL_CYCLES_RB = 2,
813 PERF_LRZ_STALL_CYCLES_VSC = 3,
814 PERF_LRZ_STALL_CYCLES_VPC = 4,
815 PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
816 PERF_LRZ_STALL_CYCLES_UCHE = 6,
817 PERF_LRZ_LRZ_READ = 7,
818 PERF_LRZ_LRZ_WRITE = 8,
819 PERF_LRZ_READ_LATENCY = 9,
820 PERF_LRZ_MERGE_CACHE_UPDATING = 10,
821 PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
822 PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
823 PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
824 PERF_LRZ_FULL_8X8_TILES = 14,
825 PERF_LRZ_PARTIAL_8X8_TILES = 15,
826 PERF_LRZ_TILE_KILLED = 16,
827 PERF_LRZ_TOTAL_PIXEL = 17,
828 PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
829 PERF_LRZ_FULLY_COVERED_TILES = 19,
830 PERF_LRZ_PARTIAL_COVERED_TILES = 20,
831 PERF_LRZ_FEEDBACK_ACCEPT = 21,
832 PERF_LRZ_FEEDBACK_DISCARD = 22,
833 PERF_LRZ_FEEDBACK_STALL = 23,
834 PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24,
835 PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25,
836 PERF_LRZ_STALL_CYCLES_VC = 26,
837 PERF_LRZ_RAS_MASK_TRANS = 27,
838 };
839
840 enum a6xx_cmp_perfcounter_select {
841 PERF_CMPDECMP_STALL_CYCLES_ARB = 0,
842 PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
843 PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
844 PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
845 PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
846 PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
847 PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
848 PERF_CMPDECMP_VBIF_READ_DATA = 7,
849 PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
850 PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
851 PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
852 PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
853 PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
854 PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
855 PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
856 PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15,
857 PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16,
858 PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17,
859 PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18,
860 PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19,
861 PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20,
862 PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21,
863 PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22,
864 PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23,
865 PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24,
866 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25,
867 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26,
868 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27,
869 PERF_CMPDECMP_2D_RD_DATA = 28,
870 PERF_CMPDECMP_2D_WR_DATA = 29,
871 PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30,
872 PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31,
873 PERF_CMPDECMP_2D_OUTPUT_TRANS = 32,
874 PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33,
875 PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34,
876 PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35,
877 PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36,
878 PERF_CMPDECMP_2D_BUSY_CYCLES = 37,
879 PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38,
880 PERF_CMPDECMP_2D_PIXELS = 39,
881 };
882
883 enum a6xx_2d_ifmt {
884 R2D_UNORM8 = 16,
885 R2D_INT32 = 7,
886 R2D_INT16 = 6,
887 R2D_INT8 = 5,
888 R2D_FLOAT32 = 4,
889 R2D_FLOAT16 = 3,
890 R2D_UNORM8_SRGB = 1,
891 R2D_RAW = 0,
892 };
893
894 enum a6xx_ztest_mode {
895 A6XX_EARLY_Z = 0,
896 A6XX_LATE_Z = 1,
897 A6XX_EARLY_LRZ_LATE_Z = 2,
898 };
899
900 enum a6xx_sequenced_thread_dist {
901 DIST_SCREEN_COORD = 0,
902 DIST_ALL_TO_RB0 = 1,
903 };
904
905 enum a6xx_single_prim_mode {
906 NO_FLUSH = 0,
907 FLUSH_PER_OVERLAP_AND_OVERWRITE = 1,
908 FLUSH_PER_OVERLAP = 3,
909 };
910
911 enum a6xx_raster_mode {
912 TYPE_TILED = 0,
913 TYPE_WRITER = 1,
914 };
915
916 enum a6xx_raster_direction {
917 LR_TB = 0,
918 RL_TB = 1,
919 LR_BT = 2,
920 RB_BT = 3,
921 };
922
923 enum a6xx_render_mode {
924 RENDERING_PASS = 0,
925 BINNING_PASS = 1,
926 };
927
928 enum a6xx_buffers_location {
929 BUFFERS_IN_GMEM = 0,
930 BUFFERS_IN_SYSMEM = 3,
931 };
932
933 enum a6xx_fragcoord_sample_mode {
934 FRAGCOORD_CENTER = 0,
935 FRAGCOORD_SAMPLE = 3,
936 };
937
938 enum a6xx_rotation {
939 ROTATE_0 = 0,
940 ROTATE_90 = 1,
941 ROTATE_180 = 2,
942 ROTATE_270 = 3,
943 ROTATE_HFLIP = 4,
944 ROTATE_VFLIP = 5,
945 };
946
947 enum a6xx_tess_spacing {
948 TESS_EQUAL = 0,
949 TESS_FRACTIONAL_ODD = 2,
950 TESS_FRACTIONAL_EVEN = 3,
951 };
952
953 enum a6xx_tess_output {
954 TESS_POINTS = 0,
955 TESS_LINES = 1,
956 TESS_CW_TRIS = 2,
957 TESS_CCW_TRIS = 3,
958 };
959
960 enum a6xx_threadsize {
961 THREAD64 = 0,
962 THREAD128 = 1,
963 };
964
965 enum a6xx_isam_mode {
966 ISAMMODE_GL = 2,
967 };
968
969 enum a6xx_tex_filter {
970 A6XX_TEX_NEAREST = 0,
971 A6XX_TEX_LINEAR = 1,
972 A6XX_TEX_ANISO = 2,
973 A6XX_TEX_CUBIC = 3,
974 };
975
976 enum a6xx_tex_clamp {
977 A6XX_TEX_REPEAT = 0,
978 A6XX_TEX_CLAMP_TO_EDGE = 1,
979 A6XX_TEX_MIRROR_REPEAT = 2,
980 A6XX_TEX_CLAMP_TO_BORDER = 3,
981 A6XX_TEX_MIRROR_CLAMP = 4,
982 };
983
984 enum a6xx_tex_aniso {
985 A6XX_TEX_ANISO_1 = 0,
986 A6XX_TEX_ANISO_2 = 1,
987 A6XX_TEX_ANISO_4 = 2,
988 A6XX_TEX_ANISO_8 = 3,
989 A6XX_TEX_ANISO_16 = 4,
990 };
991
992 enum a6xx_reduction_mode {
993 A6XX_REDUCTION_MODE_AVERAGE = 0,
994 A6XX_REDUCTION_MODE_MIN = 1,
995 A6XX_REDUCTION_MODE_MAX = 2,
996 };
997
998 enum a6xx_tex_swiz {
999 A6XX_TEX_X = 0,
1000 A6XX_TEX_Y = 1,
1001 A6XX_TEX_Z = 2,
1002 A6XX_TEX_W = 3,
1003 A6XX_TEX_ZERO = 4,
1004 A6XX_TEX_ONE = 5,
1005 };
1006
1007 enum a6xx_tex_type {
1008 A6XX_TEX_1D = 0,
1009 A6XX_TEX_2D = 1,
1010 A6XX_TEX_CUBE = 2,
1011 A6XX_TEX_3D = 3,
1012 A6XX_TEX_BUFFER = 4,
1013 };
1014
1015 #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
1016 #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002
1017 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040
1018 #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
1019 #define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100
1020 #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
1021 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
1022 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
1023 #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
1024 #define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
1025 #define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
1026 #define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000
1027 #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
1028 #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
1029 #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
1030 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
1031 #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000
1032 #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
1033 #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
1034 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
1035 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
1036 #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
1037 #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
1038 #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001
1039 #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002
1040 #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
1041 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
1042 #define A6XX_CP_INT_CP_AHB_ERROR 0x00000020
1043 #define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040
1044 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080
1045 #define REG_A6XX_CP_RB_BASE 0x00000800
1046
1047 #define REG_A6XX_CP_RB_BASE_HI 0x00000801
1048
1049 #define REG_A6XX_CP_RB_CNTL 0x00000802
1050
1051 #define REG_A6XX_CP_RB_RPTR_ADDR_LO 0x00000804
1052
1053 #define REG_A6XX_CP_RB_RPTR_ADDR_HI 0x00000805
1054
1055 #define REG_A6XX_CP_RB_RPTR 0x00000806
1056
1057 #define REG_A6XX_CP_RB_WPTR 0x00000807
1058
1059 #define REG_A6XX_CP_SQE_CNTL 0x00000808
1060
1061 #define REG_A6XX_CP_CP2GMU_STATUS 0x00000812
1062 #define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001
1063
1064 #define REG_A6XX_CP_HW_FAULT 0x00000821
1065
1066 #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823
1067
1068 #define REG_A6XX_CP_PROTECT_STATUS 0x00000824
1069
1070 #define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830
1071
1072 #define REG_A6XX_CP_MISC_CNTL 0x00000840
1073
1074 #define REG_A6XX_CP_APRIV_CNTL 0x00000844
1075
1076 #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1
1077 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK 0x000000ff
1078 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT 0
A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val)1079 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val)
1080 {
1081 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK;
1082 }
1083 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK 0x0000ff00
1084 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT 8
A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val)1085 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val)
1086 {
1087 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK;
1088 }
1089 #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000
1090 #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16
A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val)1091 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val)
1092 {
1093 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK;
1094 }
1095 #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000
1096 #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24
A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val)1097 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val)
1098 {
1099 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK;
1100 }
1101
1102 #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2
1103 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK 0x000001ff
1104 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0
A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val)1105 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val)
1106 {
1107 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK;
1108 }
1109 #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000
1110 #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16
A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val)1111 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val)
1112 {
1113 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK;
1114 }
1115
1116 #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3
1117
1118 #define REG_A6XX_CP_CHICKEN_DBG 0x00000841
1119
1120 #define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842
1121
1122 #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843
1123
1124 #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f
1125
REG_A6XX_CP_SCRATCH(uint32_t i0)1126 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }
1127
REG_A6XX_CP_SCRATCH_REG(uint32_t i0)1128 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }
1129
REG_A6XX_CP_PROTECT(uint32_t i0)1130 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; }
1131
REG_A6XX_CP_PROTECT_REG(uint32_t i0)1132 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }
1133 #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff
1134 #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)1135 static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
1136 {
1137 return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK;
1138 }
1139 #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000
1140 #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18
A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)1141 static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
1142 {
1143 return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK;
1144 }
1145 #define A6XX_CP_PROTECT_REG_READ 0x80000000
1146
1147 #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0
1148
1149 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x000008a1
1150
1151 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x000008a2
1152
1153 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x000008a3
1154
1155 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x000008a4
1156
1157 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5
1158
1159 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6
1160
1161 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7
1162
1163 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8
1164
REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0)1165 static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; }
1166
1167 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900
1168
1169 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901
1170
1171 #define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902
1172
1173 #define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903
1174
1175 #define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908
1176
1177 #define REG_A6XX_CP_SQE_STAT_DATA 0x00000909
1178
1179 #define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a
1180
1181 #define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b
1182
1183 #define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c
1184
1185 #define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d
1186
1187 #define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e
1188
1189 #define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f
1190
1191 #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910
1192
1193 #define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911
1194
1195 #define REG_A6XX_CP_IB1_BASE 0x00000928
1196
1197 #define REG_A6XX_CP_IB1_BASE_HI 0x00000929
1198
1199 #define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a
1200
1201 #define REG_A6XX_CP_IB2_BASE 0x0000092b
1202
1203 #define REG_A6XX_CP_IB2_BASE_HI 0x0000092c
1204
1205 #define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d
1206
1207 #define REG_A6XX_CP_SDS_BASE 0x0000092e
1208
1209 #define REG_A6XX_CP_SDS_BASE_HI 0x0000092f
1210
1211 #define REG_A6XX_CP_SDS_REM_SIZE 0x00000930
1212
1213 #define REG_A6XX_CP_MRB_BASE 0x00000931
1214
1215 #define REG_A6XX_CP_MRB_BASE_HI 0x00000932
1216
1217 #define REG_A6XX_CP_MRB_REM_SIZE 0x00000933
1218
1219 #define REG_A6XX_CP_VSD_BASE 0x00000934
1220
1221 #define REG_A6XX_CP_VSD_BASE_HI 0x00000935
1222
1223 #define REG_A6XX_CP_MRB_DWORDS 0x00000946
1224
1225 #define REG_A6XX_CP_VSD_DWORDS 0x00000947
1226
1227 #define REG_A6XX_CP_CSQ_IB1_STAT 0x00000949
1228 #define A6XX_CP_CSQ_IB1_STAT_REM__MASK 0xffff0000
1229 #define A6XX_CP_CSQ_IB1_STAT_REM__SHIFT 16
A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val)1230 static inline uint32_t A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val)
1231 {
1232 return ((val) << A6XX_CP_CSQ_IB1_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB1_STAT_REM__MASK;
1233 }
1234
1235 #define REG_A6XX_CP_CSQ_IB2_STAT 0x0000094a
1236 #define A6XX_CP_CSQ_IB2_STAT_REM__MASK 0xffff0000
1237 #define A6XX_CP_CSQ_IB2_STAT_REM__SHIFT 16
A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val)1238 static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val)
1239 {
1240 return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK;
1241 }
1242
1243 #define REG_A6XX_CP_MRQ_MRB_STAT 0x0000094c
1244 #define A6XX_CP_MRQ_MRB_STAT_REM__MASK 0xffff0000
1245 #define A6XX_CP_MRQ_MRB_STAT_REM__SHIFT 16
A6XX_CP_MRQ_MRB_STAT_REM(uint32_t val)1246 static inline uint32_t A6XX_CP_MRQ_MRB_STAT_REM(uint32_t val)
1247 {
1248 return ((val) << A6XX_CP_MRQ_MRB_STAT_REM__SHIFT) & A6XX_CP_MRQ_MRB_STAT_REM__MASK;
1249 }
1250
1251 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980
1252
1253 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981
1254
1255 #define REG_A6XX_CP_AHB_CNTL 0x0000098d
1256
1257 #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00
1258
1259 #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03
1260
1261 #define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34
1262
1263 #define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82
1264
1265 #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01
1266
1267 #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201
1268
1269 #define REG_A6XX_RBBM_STATUS 0x00000210
1270 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000
1271 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000
1272 #define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000
1273 #define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000
1274 #define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000
1275 #define A6XX_RBBM_STATUS_SP_BUSY 0x00040000
1276 #define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000
1277 #define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000
1278 #define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000
1279 #define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000
1280 #define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000
1281 #define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000
1282 #define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800
1283 #define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400
1284 #define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200
1285 #define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100
1286 #define A6XX_RBBM_STATUS_RB_BUSY 0x00000080
1287 #define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040
1288 #define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020
1289 #define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010
1290 #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008
1291 #define A6XX_RBBM_STATUS_CP_BUSY 0x00000004
1292 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002
1293 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001
1294
1295 #define REG_A6XX_RBBM_STATUS3 0x00000213
1296 #define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000
1297
1298 #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215
1299
REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0)1300 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; }
1301
REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0)1302 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; }
1303
REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0)1304 static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; }
1305
REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0)1306 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; }
1307
REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0)1308 static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; }
1309
REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0)1310 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; }
1311
REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0)1312 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; }
1313
REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0)1314 static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; }
1315
REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0)1316 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; }
1317
REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0)1318 static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; }
1319
REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0)1320 static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; }
1321
REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0)1322 static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; }
1323
REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0)1324 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; }
1325
REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0)1326 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; }
1327
REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0)1328 static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; }
1329
REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0)1330 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; }
1331
1332 #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500
1333
1334 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501
1335
1336 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502
1337
1338 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503
1339
1340 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504
1341
1342 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505
1343
1344 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506
1345
REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0)1346 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; }
1347
1348 #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b
1349
1350 #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD 0x0000050e
1351
1352 #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS 0x0000050f
1353
1354 #define REG_A6XX_RBBM_ISDB_CNT 0x00000533
1355
1356 #define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540
1357
1358 #define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541
1359
1360 #define REG_A6XX_RBBM_PRIMCTR_1_LO 0x00000542
1361
1362 #define REG_A6XX_RBBM_PRIMCTR_1_HI 0x00000543
1363
1364 #define REG_A6XX_RBBM_PRIMCTR_2_LO 0x00000544
1365
1366 #define REG_A6XX_RBBM_PRIMCTR_2_HI 0x00000545
1367
1368 #define REG_A6XX_RBBM_PRIMCTR_3_LO 0x00000546
1369
1370 #define REG_A6XX_RBBM_PRIMCTR_3_HI 0x00000547
1371
1372 #define REG_A6XX_RBBM_PRIMCTR_4_LO 0x00000548
1373
1374 #define REG_A6XX_RBBM_PRIMCTR_4_HI 0x00000549
1375
1376 #define REG_A6XX_RBBM_PRIMCTR_5_LO 0x0000054a
1377
1378 #define REG_A6XX_RBBM_PRIMCTR_5_HI 0x0000054b
1379
1380 #define REG_A6XX_RBBM_PRIMCTR_6_LO 0x0000054c
1381
1382 #define REG_A6XX_RBBM_PRIMCTR_6_HI 0x0000054d
1383
1384 #define REG_A6XX_RBBM_PRIMCTR_7_LO 0x0000054e
1385
1386 #define REG_A6XX_RBBM_PRIMCTR_7_HI 0x0000054f
1387
1388 #define REG_A6XX_RBBM_PRIMCTR_8_LO 0x00000550
1389
1390 #define REG_A6XX_RBBM_PRIMCTR_8_HI 0x00000551
1391
1392 #define REG_A6XX_RBBM_PRIMCTR_9_LO 0x00000552
1393
1394 #define REG_A6XX_RBBM_PRIMCTR_9_HI 0x00000553
1395
1396 #define REG_A6XX_RBBM_PRIMCTR_10_LO 0x00000554
1397
1398 #define REG_A6XX_RBBM_PRIMCTR_10_HI 0x00000555
1399
1400 #define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
1401
1402 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
1403
1404 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
1405
1406 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
1407
1408 #define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803
1409
1410 #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
1411
1412 #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010
1413
1414 #define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011
1415
1416 #define REG_A6XX_RBBM_GBIF_HALT 0x00000016
1417
1418 #define REG_A6XX_RBBM_GBIF_HALT_ACK 0x00000017
1419
1420 #define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD 0x0000001c
1421 #define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE 0x00000001
1422
1423 #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f
1424
1425 #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037
1426
1427 #define REG_A6XX_RBBM_INT_0_MASK 0x00000038
1428
1429 #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042
1430
1431 #define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043
1432
1433 #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044
1434
1435 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1436
1437 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
1438
1439 #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae
1440
1441 #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0
1442
1443 #define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1
1444
1445 #define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2
1446
1447 #define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3
1448
1449 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4
1450
1451 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5
1452
1453 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6
1454
1455 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7
1456
1457 #define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8
1458
1459 #define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9
1460
1461 #define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba
1462
1463 #define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb
1464
1465 #define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc
1466
1467 #define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd
1468
1469 #define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be
1470
1471 #define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf
1472
1473 #define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0
1474
1475 #define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1
1476
1477 #define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2
1478
1479 #define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3
1480
1481 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4
1482
1483 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5
1484
1485 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6
1486
1487 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7
1488
1489 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8
1490
1491 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9
1492
1493 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca
1494
1495 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb
1496
1497 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc
1498
1499 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd
1500
1501 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce
1502
1503 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf
1504
1505 #define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0
1506
1507 #define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1
1508
1509 #define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2
1510
1511 #define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3
1512
1513 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4
1514
1515 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5
1516
1517 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6
1518
1519 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7
1520
1521 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8
1522
1523 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9
1524
1525 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da
1526
1527 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db
1528
1529 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc
1530
1531 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd
1532
1533 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de
1534
1535 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df
1536
1537 #define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0
1538
1539 #define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1
1540
1541 #define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2
1542
1543 #define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3
1544
1545 #define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4
1546
1547 #define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5
1548
1549 #define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6
1550
1551 #define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7
1552
1553 #define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8
1554
1555 #define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9
1556
1557 #define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea
1558
1559 #define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb
1560
1561 #define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec
1562
1563 #define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed
1564
1565 #define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee
1566
1567 #define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef
1568
1569 #define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0
1570
1571 #define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1
1572
1573 #define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2
1574
1575 #define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3
1576
1577 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4
1578
1579 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5
1580
1581 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6
1582
1583 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7
1584
1585 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8
1586
1587 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9
1588
1589 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa
1590
1591 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb
1592
1593 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100
1594
1595 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101
1596
1597 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102
1598
1599 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103
1600
1601 #define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104
1602
1603 #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105
1604
1605 #define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106
1606
1607 #define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107
1608
1609 #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108
1610
1611 #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109
1612
1613 #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a
1614
1615 #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b
1616
1617 #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c
1618
1619 #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d
1620
1621 #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e
1622
1623 #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f
1624
1625 #define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110
1626
1627 #define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111
1628
1629 #define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112
1630
1631 #define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113
1632
1633 #define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114
1634
1635 #define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115
1636
1637 #define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116
1638
1639 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117
1640
1641 #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118
1642
1643 #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119
1644
1645 #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a
1646
1647 #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b
1648
1649 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c
1650
1651 #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d
1652
1653 #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120
1654
1655 #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121
1656
1657 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122
1658
1659 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600
1660
1661 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601
1662
1663 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602
1664
1665 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603
1666 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff
1667 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0
A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)1668 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)
1669 {
1670 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK;
1671 }
1672 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00
1673 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8
A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)1674 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)
1675 {
1676 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK;
1677 }
1678
1679 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604
1680 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
1681 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)1682 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
1683 {
1684 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
1685 }
1686 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
1687 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)1688 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
1689 {
1690 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
1691 }
1692 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
1693 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)1694 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
1695 {
1696 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
1697 }
1698
1699 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605
1700 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
1701 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)1702 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
1703 {
1704 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
1705 }
1706
1707 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608
1708
1709 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609
1710
1711 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a
1712
1713 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b
1714
1715 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c
1716
1717 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d
1718
1719 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e
1720
1721 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f
1722
1723 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610
1724 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
1725 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)1726 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
1727 {
1728 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
1729 }
1730 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
1731 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)1732 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
1733 {
1734 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
1735 }
1736 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
1737 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)1738 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
1739 {
1740 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
1741 }
1742 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
1743 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)1744 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
1745 {
1746 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
1747 }
1748 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
1749 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)1750 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
1751 {
1752 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
1753 }
1754 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
1755 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)1756 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
1757 {
1758 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
1759 }
1760 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
1761 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)1762 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
1763 {
1764 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
1765 }
1766 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
1767 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)1768 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
1769 {
1770 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
1771 }
1772
1773 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611
1774 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
1775 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)1776 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
1777 {
1778 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
1779 }
1780 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
1781 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)1782 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
1783 {
1784 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
1785 }
1786 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
1787 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)1788 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
1789 {
1790 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
1791 }
1792 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
1793 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)1794 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
1795 {
1796 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
1797 }
1798 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
1799 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)1800 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
1801 {
1802 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
1803 }
1804 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
1805 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)1806 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
1807 {
1808 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
1809 }
1810 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
1811 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)1812 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
1813 {
1814 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
1815 }
1816 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
1817 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)1818 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
1819 {
1820 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
1821 }
1822
1823 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f
1824
1825 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630
1826
REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0)1827 static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; }
1828
1829 #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800
1830
1831 #define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000
1832
1833 #define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00
1834
1835 #define REG_A6XX_UCHE_MODE_CNTL 0x00000e01
1836
1837 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05
1838
1839 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06
1840
1841 #define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07
1842
1843 #define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08
1844
1845 #define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09
1846
1847 #define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a
1848
1849 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b
1850
1851 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c
1852
1853 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d
1854
1855 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e
1856
1857 #define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17
1858
1859 #define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18
1860
1861 #define REG_A6XX_UCHE_CLIENT_PF 0x00000e19
1862 #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff
1863 #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0
A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)1864 static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
1865 {
1866 return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
1867 }
1868
REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0)1869 static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; }
1870
1871 #define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c
1872
1873 #define REG_A6XX_VBIF_VERSION 0x00003000
1874
1875 #define REG_A6XX_VBIF_CLKON 0x00003001
1876 #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002
1877
1878 #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
1879
1880 #define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080
1881
1882 #define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081
1883
1884 #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
1885
1886 #define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085
1887
1888 #define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086
1889 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f
1890 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0
A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)1891 static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)
1892 {
1893 return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK;
1894 }
1895
1896 #define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087
1897
1898 #define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088
1899 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff
1900 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0
A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)1901 static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
1902 {
1903 return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK;
1904 }
1905
1906 #define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c
1907
1908 #define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0
1909
1910 #define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1
1911
1912 #define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2
1913
1914 #define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3
1915
1916 #define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8
1917
1918 #define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9
1919
1920 #define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da
1921
1922 #define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db
1923
1924 #define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0
1925
1926 #define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1
1927
1928 #define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2
1929
1930 #define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3
1931
1932 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
1933
1934 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
1935
1936 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
1937
1938 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
1939
1940 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
1941
1942 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
1943
1944 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
1945
1946 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
1947
1948 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
1949
1950 #define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01
1951
1952 #define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02
1953
1954 #define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03
1955
1956 #define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04
1957
1958 #define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05
1959
1960 #define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06
1961
1962 #define REG_A6XX_GBIF_HALT 0x00003c45
1963
1964 #define REG_A6XX_GBIF_HALT_ACK 0x00003c46
1965
1966 #define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0
1967
1968 #define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2
1969
1970 #define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3
1971
1972 #define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4
1973
1974 #define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5
1975
1976 #define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6
1977
1978 #define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7
1979
1980 #define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8
1981
1982 #define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9
1983
1984 #define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca
1985
1986 #define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb
1987
1988 #define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc
1989
1990 #define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd
1991
1992 #define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce
1993
1994 #define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf
1995
1996 #define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0
1997
1998 #define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1
1999
2000 #define REG_A6XX_VSC_DBG_ECO_CNTL 0x00000c00
2001
2002 #define REG_A6XX_VSC_BIN_SIZE 0x00000c02
2003 #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
2004 #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)2005 static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2006 {
2007 return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK;
2008 }
2009 #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00
2010 #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8
A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)2011 static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2012 {
2013 return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
2014 }
2015
2016 #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03
2017
2018 #define REG_A6XX_VSC_BIN_COUNT 0x00000c06
2019 #define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe
2020 #define A6XX_VSC_BIN_COUNT_NX__SHIFT 1
A6XX_VSC_BIN_COUNT_NX(uint32_t val)2021 static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val)
2022 {
2023 return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK;
2024 }
2025 #define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800
2026 #define A6XX_VSC_BIN_COUNT_NY__SHIFT 11
A6XX_VSC_BIN_COUNT_NY(uint32_t val)2027 static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val)
2028 {
2029 return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK;
2030 }
2031
REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0)2032 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2033
REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0)2034 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2035 #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
2036 #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)2037 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
2038 {
2039 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK;
2040 }
2041 #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
2042 #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)2043 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
2044 {
2045 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK;
2046 }
2047 #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000
2048 #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)2049 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
2050 {
2051 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK;
2052 }
2053 #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000
2054 #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26
A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)2055 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2056 {
2057 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
2058 }
2059
2060 #define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30
2061
2062 #define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32
2063
2064 #define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33
2065
2066 #define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34
2067
2068 #define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36
2069
2070 #define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37
2071
REG_A6XX_VSC_STATE(uint32_t i0)2072 static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
2073
REG_A6XX_VSC_STATE_REG(uint32_t i0)2074 static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
2075
REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0)2076 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
2077
REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0)2078 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
2079
REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0)2080 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2081
REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0)2082 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2083
2084 #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12
2085
2086 #define REG_A6XX_GRAS_CL_CNTL 0x00008000
2087 #define A6XX_GRAS_CL_CNTL_CLIP_DISABLE 0x00000001
2088 #define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE 0x00000002
2089 #define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE 0x00000004
2090 #define A6XX_GRAS_CL_CNTL_UNK5 0x00000020
2091 #define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
2092 #define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE 0x00000080
2093 #define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE 0x00000100
2094 #define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE 0x00000200
2095
2096 #define REG_A6XX_GRAS_VS_CL_CNTL 0x00008001
2097 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
2098 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0
A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)2099 static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
2100 {
2101 return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
2102 }
2103 #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
2104 #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8
A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)2105 static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
2106 {
2107 return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
2108 }
2109
2110 #define REG_A6XX_GRAS_DS_CL_CNTL 0x00008002
2111 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
2112 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT 0
A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val)2113 static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val)
2114 {
2115 return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK;
2116 }
2117 #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
2118 #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT 8
A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val)2119 static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val)
2120 {
2121 return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK;
2122 }
2123
2124 #define REG_A6XX_GRAS_GS_CL_CNTL 0x00008003
2125 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
2126 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT 0
A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val)2127 static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val)
2128 {
2129 return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK;
2130 }
2131 #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
2132 #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT 8
A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val)2133 static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val)
2134 {
2135 return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK;
2136 }
2137
2138 #define REG_A6XX_GRAS_MAX_LAYER_INDEX 0x00008004
2139
2140 #define REG_A6XX_GRAS_CNTL 0x00008005
2141 #define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
2142 #define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
2143 #define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
2144 #define A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL 0x00000008
2145 #define A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID 0x00000010
2146 #define A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE 0x00000020
2147 #define A6XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0
2148 #define A6XX_GRAS_CNTL_COORD_MASK__SHIFT 6
A6XX_GRAS_CNTL_COORD_MASK(uint32_t val)2149 static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val)
2150 {
2151 return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK;
2152 }
2153
2154 #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006
2155 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff
2156 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)2157 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
2158 {
2159 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
2160 }
2161 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x0007fc00
2162 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)2163 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
2164 {
2165 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
2166 }
2167
REG_A6XX_GRAS_CL_VPORT(uint32_t i0)2168 static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; }
2169
REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0)2170 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; }
2171 #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff
2172 #define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0
A6XX_GRAS_CL_VPORT_XOFFSET(float val)2173 static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val)
2174 {
2175 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK;
2176 }
2177
REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0)2178 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; }
2179 #define A6XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff
2180 #define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT 0
A6XX_GRAS_CL_VPORT_XSCALE(float val)2181 static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val)
2182 {
2183 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK;
2184 }
2185
REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0)2186 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; }
2187 #define A6XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff
2188 #define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0
A6XX_GRAS_CL_VPORT_YOFFSET(float val)2189 static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val)
2190 {
2191 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK;
2192 }
2193
REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0)2194 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; }
2195 #define A6XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff
2196 #define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT 0
A6XX_GRAS_CL_VPORT_YSCALE(float val)2197 static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val)
2198 {
2199 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK;
2200 }
2201
REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0)2202 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; }
2203 #define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff
2204 #define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0
A6XX_GRAS_CL_VPORT_ZOFFSET(float val)2205 static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val)
2206 {
2207 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK;
2208 }
2209
REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0)2210 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; }
2211 #define A6XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff
2212 #define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0
A6XX_GRAS_CL_VPORT_ZSCALE(float val)2213 static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val)
2214 {
2215 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK;
2216 }
2217
REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0)2218 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; }
2219
REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0)2220 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; }
2221 #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff
2222 #define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT 0
A6XX_GRAS_CL_Z_CLAMP_MIN(float val)2223 static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val)
2224 {
2225 return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK;
2226 }
2227
REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0)2228 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; }
2229 #define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK 0xffffffff
2230 #define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT 0
A6XX_GRAS_CL_Z_CLAMP_MAX(float val)2231 static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val)
2232 {
2233 return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK;
2234 }
2235
2236 #define REG_A6XX_GRAS_SU_CNTL 0x00008090
2237 #define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
2238 #define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
2239 #define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
2240 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
2241 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)2242 static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
2243 {
2244 return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2245 }
2246 #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
2247 #define A6XX_GRAS_SU_CNTL_UNK12__MASK 0x00001000
2248 #define A6XX_GRAS_SU_CNTL_UNK12__SHIFT 12
A6XX_GRAS_SU_CNTL_UNK12(uint32_t val)2249 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val)
2250 {
2251 return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK;
2252 }
2253 #define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK 0x00002000
2254 #define A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT 13
A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val)2255 static inline uint32_t A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val)
2256 {
2257 return ((val) << A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A6XX_GRAS_SU_CNTL_LINE_MODE__MASK;
2258 }
2259 #define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000
2260 #define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15
A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)2261 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)
2262 {
2263 return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK;
2264 }
2265 #define A6XX_GRAS_SU_CNTL_UNK17 0x00020000
2266 #define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000
2267 #define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000
2268 #define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19
A6XX_GRAS_SU_CNTL_UNK19(uint32_t val)2269 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val)
2270 {
2271 return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK;
2272 }
2273
2274 #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091
2275 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2276 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)2277 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2278 {
2279 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2280 }
2281 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2282 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
A6XX_GRAS_SU_POINT_MINMAX_MAX(float val)2283 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2284 {
2285 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2286 }
2287
2288 #define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092
2289 #define A6XX_GRAS_SU_POINT_SIZE__MASK 0x0000ffff
2290 #define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0
A6XX_GRAS_SU_POINT_SIZE(float val)2291 static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
2292 {
2293 return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK;
2294 }
2295
2296 #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094
2297 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003
2298 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0
A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)2299 static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
2300 {
2301 return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK;
2302 }
2303
2304 #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095
2305 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2306 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val)2307 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2308 {
2309 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2310 }
2311
2312 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096
2313 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2314 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)2315 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2316 {
2317 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2318 }
2319
2320 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097
2321 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
2322 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)2323 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2324 {
2325 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2326 }
2327
2328 #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098
2329 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2330 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)2331 static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
2332 {
2333 return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2334 }
2335 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000008
2336 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT 3
A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val)2337 static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
2338 {
2339 return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK;
2340 }
2341
2342 #define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x00008099
2343 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001
2344 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK 0x00000006
2345 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT 1
A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(uint32_t val)2346 static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(uint32_t val)
2347 {
2348 return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK;
2349 }
2350 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN 0x00000008
2351 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK 0x00000030
2352 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT 4
A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(uint32_t val)2353 static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(uint32_t val)
2354 {
2355 return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK;
2356 }
2357
2358 #define REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL 0x0000809a
2359 #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 0x00000001
2360 #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN 0x00000002
2361
2362 #define REG_A6XX_GRAS_VS_LAYER_CNTL 0x0000809b
2363 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER 0x00000001
2364 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW 0x00000002
2365
2366 #define REG_A6XX_GRAS_GS_LAYER_CNTL 0x0000809c
2367 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER 0x00000001
2368 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW 0x00000002
2369
2370 #define REG_A6XX_GRAS_DS_LAYER_CNTL 0x0000809d
2371 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER 0x00000001
2372 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW 0x00000002
2373
2374 #define REG_A6XX_GRAS_SC_CNTL 0x000080a0
2375 #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000007
2376 #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT 0
A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(uint32_t val)2377 static inline uint32_t A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(uint32_t val)
2378 {
2379 return ((val) << A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK;
2380 }
2381 #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK 0x00000018
2382 #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT 3
A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val)2383 static inline uint32_t A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val)
2384 {
2385 return ((val) << A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK;
2386 }
2387 #define A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK 0x00000020
2388 #define A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT 5
A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val)2389 static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
2390 {
2391 return ((val) << A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK;
2392 }
2393 #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK 0x000000c0
2394 #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT 6
A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)2395 static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)
2396 {
2397 return ((val) << A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK;
2398 }
2399 #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK 0x00000100
2400 #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT 8
A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val)2401 static inline uint32_t A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val)
2402 {
2403 return ((val) << A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT) & A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK;
2404 }
2405 #define A6XX_GRAS_SC_CNTL_UNK9__MASK 0x00000e00
2406 #define A6XX_GRAS_SC_CNTL_UNK9__SHIFT 9
A6XX_GRAS_SC_CNTL_UNK9(uint32_t val)2407 static inline uint32_t A6XX_GRAS_SC_CNTL_UNK9(uint32_t val)
2408 {
2409 return ((val) << A6XX_GRAS_SC_CNTL_UNK9__SHIFT) & A6XX_GRAS_SC_CNTL_UNK9__MASK;
2410 }
2411 #define A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN 0x00001000
2412
2413 #define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1
2414 #define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x0000003f
2415 #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0
A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)2416 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)
2417 {
2418 return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK;
2419 }
2420 #define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00
2421 #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8
A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)2422 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)
2423 {
2424 return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK;
2425 }
2426 #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000
2427 #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT 18
A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)2428 static inline uint32_t A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)
2429 {
2430 return ((val) << A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK;
2431 }
2432 #define A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000
2433 #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000
2434 #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22
A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val)2435 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val)
2436 {
2437 return ((val) << A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK;
2438 }
2439 #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000
2440 #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24
A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)2441 static inline uint32_t A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)
2442 {
2443 return ((val) << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK;
2444 }
2445 #define A6XX_GRAS_BIN_CONTROL_UNK27__MASK 0x08000000
2446 #define A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT 27
A6XX_GRAS_BIN_CONTROL_UNK27(uint32_t val)2447 static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK27(uint32_t val)
2448 {
2449 return ((val) << A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK27__MASK;
2450 }
2451
2452 #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2
2453 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2454 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)2455 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2456 {
2457 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK;
2458 }
2459 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK 0x00000004
2460 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT 2
A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val)2461 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val)
2462 {
2463 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK;
2464 }
2465 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK 0x00000008
2466 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT 3
A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val)2467 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val)
2468 {
2469 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK;
2470 }
2471
2472 #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3
2473 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2474 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)2475 static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2476 {
2477 return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK;
2478 }
2479 #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2480
2481 #define REG_A6XX_GRAS_SAMPLE_CONFIG 0x000080a4
2482 #define A6XX_GRAS_SAMPLE_CONFIG_UNK0 0x00000001
2483 #define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
2484
2485 #define REG_A6XX_GRAS_SAMPLE_LOCATION_0 0x000080a5
2486 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
2487 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)2488 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
2489 {
2490 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
2491 }
2492 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
2493 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)2494 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
2495 {
2496 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
2497 }
2498 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
2499 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)2500 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
2501 {
2502 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
2503 }
2504 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
2505 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)2506 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
2507 {
2508 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
2509 }
2510 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
2511 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)2512 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
2513 {
2514 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
2515 }
2516 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
2517 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)2518 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
2519 {
2520 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
2521 }
2522 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
2523 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)2524 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
2525 {
2526 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
2527 }
2528 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
2529 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)2530 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
2531 {
2532 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
2533 }
2534
2535 #define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6
2536 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
2537 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)2538 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
2539 {
2540 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
2541 }
2542 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
2543 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)2544 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
2545 {
2546 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
2547 }
2548 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
2549 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)2550 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
2551 {
2552 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
2553 }
2554 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
2555 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)2556 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
2557 {
2558 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
2559 }
2560 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
2561 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)2562 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
2563 {
2564 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
2565 }
2566 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
2567 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)2568 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
2569 {
2570 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
2571 }
2572 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
2573 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)2574 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
2575 {
2576 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
2577 }
2578 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
2579 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)2580 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
2581 {
2582 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
2583 }
2584
2585 #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af
2586
REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0)2587 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
2588
REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0)2589 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
2590 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff
2591 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)2592 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
2593 {
2594 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
2595 }
2596 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0xffff0000
2597 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)2598 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
2599 {
2600 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
2601 }
2602
REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0)2603 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; }
2604 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x0000ffff
2605 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)2606 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
2607 {
2608 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
2609 }
2610 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0xffff0000
2611 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)2612 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
2613 {
2614 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
2615 }
2616
REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0)2617 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
2618
REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0)2619 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
2620 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff
2621 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT 0
A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val)2622 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val)
2623 {
2624 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK;
2625 }
2626 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK 0xffff0000
2627 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT 16
A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val)2628 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val)
2629 {
2630 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK;
2631 }
2632
REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0)2633 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; }
2634 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK 0x0000ffff
2635 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT 0
A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val)2636 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val)
2637 {
2638 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK;
2639 }
2640 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK 0xffff0000
2641 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT 16
A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val)2642 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val)
2643 {
2644 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK;
2645 }
2646
2647 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0
2648 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00003fff
2649 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)2650 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2651 {
2652 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2653 }
2654 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x3fff0000
2655 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)2656 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2657 {
2658 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2659 }
2660
2661 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1
2662 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00003fff
2663 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)2664 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2665 {
2666 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2667 }
2668 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x3fff0000
2669 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)2670 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2671 {
2672 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2673 }
2674
2675 #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100
2676 #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
2677 #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
2678 #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
2679 #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008
2680 #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010
2681 #define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020
2682 #define A6XX_GRAS_LRZ_CNTL_UNK6__MASK 0x000003c0
2683 #define A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT 6
A6XX_GRAS_LRZ_CNTL_UNK6(uint32_t val)2684 static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK6(uint32_t val)
2685 {
2686 return ((val) << A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK6__MASK;
2687 }
2688
2689 #define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL 0x00008101
2690 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID 0x00000001
2691 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK 0x00000006
2692 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT 1
A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val)2693 static inline uint32_t A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val)
2694 {
2695 return ((val) << A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK;
2696 }
2697
2698 #define REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0 0x00008102
2699 #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK 0x000000ff
2700 #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT 0
A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val)2701 static inline uint32_t A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val)
2702 {
2703 return ((val) << A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT) & A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK;
2704 }
2705
2706 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103
2707 #define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff
2708 #define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0
A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val)2709 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val)
2710 {
2711 return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK;
2712 }
2713
2714 #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105
2715 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff
2716 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0
A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)2717 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)
2718 {
2719 return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK;
2720 }
2721 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00
2722 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10
A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)2723 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
2724 {
2725 return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
2726 }
2727
2728 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106
2729 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff
2730 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0
A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val)2731 static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val)
2732 {
2733 return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK;
2734 }
2735
2736 #define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109
2737 #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
2738
2739 #define REG_A6XX_GRAS_UNKNOWN_810A 0x0000810a
2740 #define A6XX_GRAS_UNKNOWN_810A_UNK0__MASK 0x000007ff
2741 #define A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT 0
A6XX_GRAS_UNKNOWN_810A_UNK0(uint32_t val)2742 static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK0(uint32_t val)
2743 {
2744 return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK0__MASK;
2745 }
2746 #define A6XX_GRAS_UNKNOWN_810A_UNK16__MASK 0x07ff0000
2747 #define A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT 16
A6XX_GRAS_UNKNOWN_810A_UNK16(uint32_t val)2748 static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK16(uint32_t val)
2749 {
2750 return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK16__MASK;
2751 }
2752 #define A6XX_GRAS_UNKNOWN_810A_UNK28__MASK 0xf0000000
2753 #define A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT 28
A6XX_GRAS_UNKNOWN_810A_UNK28(uint32_t val)2754 static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK28(uint32_t val)
2755 {
2756 return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK28__MASK;
2757 }
2758
2759 #define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110
2760
2761 #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400
2762 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007
2763 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0
A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)2764 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
2765 {
2766 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK;
2767 }
2768 #define A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN 0x00000008
2769 #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK 0x00000070
2770 #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT 4
A6XX_GRAS_2D_BLIT_CNTL_UNK4(uint32_t val)2771 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK4(uint32_t val)
2772 {
2773 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK;
2774 }
2775 #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000080
2776 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
2777 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)2778 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
2779 {
2780 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
2781 }
2782 #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000
2783 #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK 0x00060000
2784 #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT 17
A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val)2785 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val)
2786 {
2787 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK;
2788 }
2789 #define A6XX_GRAS_2D_BLIT_CNTL_D24S8 0x00080000
2790 #define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK 0x00f00000
2791 #define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT 20
A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val)2792 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val)
2793 {
2794 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK;
2795 }
2796 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000
2797 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24
A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)2798 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
2799 {
2800 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK;
2801 }
2802 #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000
2803 #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29
A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val)2804 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
2805 {
2806 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK;
2807 }
2808
2809 #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401
2810
2811 #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402
2812
2813 #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403
2814
2815 #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404
2816
2817 #define REG_A6XX_GRAS_2D_DST_TL 0x00008405
2818 #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff
2819 #define A6XX_GRAS_2D_DST_TL_X__SHIFT 0
A6XX_GRAS_2D_DST_TL_X(uint32_t val)2820 static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val)
2821 {
2822 return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK;
2823 }
2824 #define A6XX_GRAS_2D_DST_TL_Y__MASK 0x3fff0000
2825 #define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16
A6XX_GRAS_2D_DST_TL_Y(uint32_t val)2826 static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val)
2827 {
2828 return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK;
2829 }
2830
2831 #define REG_A6XX_GRAS_2D_DST_BR 0x00008406
2832 #define A6XX_GRAS_2D_DST_BR_X__MASK 0x00003fff
2833 #define A6XX_GRAS_2D_DST_BR_X__SHIFT 0
A6XX_GRAS_2D_DST_BR_X(uint32_t val)2834 static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val)
2835 {
2836 return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK;
2837 }
2838 #define A6XX_GRAS_2D_DST_BR_Y__MASK 0x3fff0000
2839 #define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16
A6XX_GRAS_2D_DST_BR_Y(uint32_t val)2840 static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val)
2841 {
2842 return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK;
2843 }
2844
2845 #define REG_A6XX_GRAS_2D_UNKNOWN_8407 0x00008407
2846
2847 #define REG_A6XX_GRAS_2D_UNKNOWN_8408 0x00008408
2848
2849 #define REG_A6XX_GRAS_2D_UNKNOWN_8409 0x00008409
2850
2851 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 0x0000840a
2852 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK 0x00003fff
2853 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT 0
A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val)2854 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val)
2855 {
2856 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK;
2857 }
2858 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK 0x3fff0000
2859 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT 16
A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val)2860 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val)
2861 {
2862 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK;
2863 }
2864
2865 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 0x0000840b
2866 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK 0x00003fff
2867 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT 0
A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val)2868 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val)
2869 {
2870 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK;
2871 }
2872 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK 0x3fff0000
2873 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT 16
A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val)2874 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val)
2875 {
2876 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK;
2877 }
2878
2879 #define REG_A6XX_GRAS_DBG_ECO_CNTL 0x00008600
2880 #define A6XX_GRAS_DBG_ECO_CNTL_UNK7 0x00000080
2881 #define A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS 0x00000800
2882
2883 #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601
2884
REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0)2885 static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; }
2886
REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0)2887 static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; }
2888
REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0)2889 static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; }
2890
2891 #define REG_A6XX_RB_BIN_CONTROL 0x00008800
2892 #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f
2893 #define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0
A6XX_RB_BIN_CONTROL_BINW(uint32_t val)2894 static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
2895 {
2896 return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
2897 }
2898 #define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00
2899 #define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8
A6XX_RB_BIN_CONTROL_BINH(uint32_t val)2900 static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val)
2901 {
2902 return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK;
2903 }
2904 #define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000
2905 #define A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18
A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)2906 static inline uint32_t A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)
2907 {
2908 return ((val) << A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK;
2909 }
2910 #define A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000
2911 #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000
2912 #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22
A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val)2913 static inline uint32_t A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val)
2914 {
2915 return ((val) << A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK;
2916 }
2917 #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000
2918 #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24
A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)2919 static inline uint32_t A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)
2920 {
2921 return ((val) << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK;
2922 }
2923
2924 #define REG_A6XX_RB_RENDER_CNTL 0x00008801
2925 #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000038
2926 #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT 3
A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(uint32_t val)2927 static inline uint32_t A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(uint32_t val)
2928 {
2929 return ((val) << A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK;
2930 }
2931 #define A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN 0x00000040
2932 #define A6XX_RB_RENDER_CNTL_BINNING 0x00000080
2933 #define A6XX_RB_RENDER_CNTL_UNK8__MASK 0x00000700
2934 #define A6XX_RB_RENDER_CNTL_UNK8__SHIFT 8
A6XX_RB_RENDER_CNTL_UNK8(uint32_t val)2935 static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val)
2936 {
2937 return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK;
2938 }
2939 #define A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK 0x00000100
2940 #define A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT 8
A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val)2941 static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
2942 {
2943 return ((val) << A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK;
2944 }
2945 #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK 0x00000600
2946 #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT 9
A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)2947 static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)
2948 {
2949 return ((val) << A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK;
2950 }
2951 #define A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN 0x00000800
2952 #define A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN 0x00001000
2953 #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
2954 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
2955 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)2956 static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
2957 {
2958 return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
2959 }
2960
2961 #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802
2962 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2963 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)2964 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2965 {
2966 return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
2967 }
2968 #define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK 0x00000004
2969 #define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT 2
A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val)2970 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val)
2971 {
2972 return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK;
2973 }
2974 #define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK 0x00000008
2975 #define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT 3
A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val)2976 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val)
2977 {
2978 return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK;
2979 }
2980
2981 #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803
2982 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2983 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)2984 static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2985 {
2986 return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
2987 }
2988 #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2989
2990 #define REG_A6XX_RB_SAMPLE_CONFIG 0x00008804
2991 #define A6XX_RB_SAMPLE_CONFIG_UNK0 0x00000001
2992 #define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
2993
2994 #define REG_A6XX_RB_SAMPLE_LOCATION_0 0x00008805
2995 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
2996 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)2997 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
2998 {
2999 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
3000 }
3001 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
3002 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)3003 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
3004 {
3005 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
3006 }
3007 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
3008 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)3009 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
3010 {
3011 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
3012 }
3013 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
3014 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)3015 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
3016 {
3017 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
3018 }
3019 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
3020 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)3021 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
3022 {
3023 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
3024 }
3025 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
3026 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)3027 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
3028 {
3029 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
3030 }
3031 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
3032 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)3033 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
3034 {
3035 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
3036 }
3037 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
3038 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)3039 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
3040 {
3041 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
3042 }
3043
3044 #define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806
3045 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
3046 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)3047 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
3048 {
3049 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
3050 }
3051 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
3052 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)3053 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
3054 {
3055 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
3056 }
3057 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
3058 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)3059 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
3060 {
3061 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
3062 }
3063 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
3064 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)3065 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
3066 {
3067 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
3068 }
3069 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
3070 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)3071 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
3072 {
3073 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
3074 }
3075 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
3076 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)3077 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
3078 {
3079 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
3080 }
3081 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
3082 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)3083 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
3084 {
3085 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
3086 }
3087 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
3088 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)3089 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
3090 {
3091 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
3092 }
3093
3094 #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809
3095 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001
3096 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002
3097 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004
3098 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL 0x00000008
3099 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID 0x00000010
3100 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE 0x00000020
3101 #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0
3102 #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6
A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)3103 static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
3104 {
3105 return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
3106 }
3107 #define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400
3108
3109 #define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a
3110 #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
3111 #define A6XX_RB_RENDER_CONTROL1_UNK1 0x00000002
3112 #define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004
3113 #define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008
3114 #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK 0x00000030
3115 #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT 4
A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val)3116 static inline uint32_t A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val)
3117 {
3118 return ((val) << A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK;
3119 }
3120 #define A6XX_RB_RENDER_CONTROL1_SIZE 0x00000040
3121 #define A6XX_RB_RENDER_CONTROL1_LINELENGTHEN 0x00000080
3122 #define A6XX_RB_RENDER_CONTROL1_FOVEATION 0x00000100
3123
3124 #define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b
3125 #define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001
3126 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002
3127 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004
3128 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF 0x00000008
3129
3130 #define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c
3131 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
3132 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0
A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val)3133 static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val)
3134 {
3135 return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK;
3136 }
3137
3138 #define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d
3139 #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
3140 #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)3141 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
3142 {
3143 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK;
3144 }
3145 #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
3146 #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)3147 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
3148 {
3149 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK;
3150 }
3151 #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
3152 #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)3153 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
3154 {
3155 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK;
3156 }
3157 #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
3158 #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)3159 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
3160 {
3161 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK;
3162 }
3163 #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
3164 #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)3165 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
3166 {
3167 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK;
3168 }
3169 #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
3170 #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)3171 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
3172 {
3173 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK;
3174 }
3175 #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
3176 #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)3177 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
3178 {
3179 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK;
3180 }
3181 #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
3182 #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)3183 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
3184 {
3185 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK;
3186 }
3187
3188 #define REG_A6XX_RB_DITHER_CNTL 0x0000880e
3189 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003
3190 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val)3191 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val)
3192 {
3193 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK;
3194 }
3195 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c
3196 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val)3197 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val)
3198 {
3199 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK;
3200 }
3201 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030
3202 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val)3203 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val)
3204 {
3205 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK;
3206 }
3207 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0
3208 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val)3209 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val)
3210 {
3211 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK;
3212 }
3213 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300
3214 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val)3215 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val)
3216 {
3217 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK;
3218 }
3219 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00
3220 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val)3221 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val)
3222 {
3223 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK;
3224 }
3225 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000
3226 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)3227 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)
3228 {
3229 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK;
3230 }
3231 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000
3232 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val)3233 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val)
3234 {
3235 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK;
3236 }
3237
3238 #define REG_A6XX_RB_SRGB_CNTL 0x0000880f
3239 #define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001
3240 #define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002
3241 #define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004
3242 #define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008
3243 #define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010
3244 #define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020
3245 #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040
3246 #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080
3247
3248 #define REG_A6XX_RB_SAMPLE_CNTL 0x00008810
3249 #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
3250
3251 #define REG_A6XX_RB_UNKNOWN_8811 0x00008811
3252
3253 #define REG_A6XX_RB_UNKNOWN_8818 0x00008818
3254
3255 #define REG_A6XX_RB_UNKNOWN_8819 0x00008819
3256
3257 #define REG_A6XX_RB_UNKNOWN_881A 0x0000881a
3258
3259 #define REG_A6XX_RB_UNKNOWN_881B 0x0000881b
3260
3261 #define REG_A6XX_RB_UNKNOWN_881C 0x0000881c
3262
3263 #define REG_A6XX_RB_UNKNOWN_881D 0x0000881d
3264
3265 #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e
3266
REG_A6XX_RB_MRT(uint32_t i0)3267 static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; }
3268
REG_A6XX_RB_MRT_CONTROL(uint32_t i0)3269 static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }
3270 #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001
3271 #define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002
3272 #define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004
3273 #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078
3274 #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3
A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)3275 static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
3276 {
3277 return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK;
3278 }
3279 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
3280 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)3281 static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
3282 {
3283 return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
3284 }
3285
REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0)3286 static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; }
3287 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
3288 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)3289 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
3290 {
3291 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
3292 }
3293 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
3294 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)3295 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3296 {
3297 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
3298 }
3299 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
3300 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)3301 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
3302 {
3303 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
3304 }
3305 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
3306 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)3307 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
3308 {
3309 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
3310 }
3311 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
3312 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)3313 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3314 {
3315 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
3316 }
3317 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
3318 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)3319 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
3320 {
3321 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
3322 }
3323
REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0)3324 static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }
3325 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
3326 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val)3327 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val)
3328 {
3329 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
3330 }
3331 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
3332 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)3333 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)
3334 {
3335 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
3336 }
3337 #define A6XX_RB_MRT_BUF_INFO_UNK10__MASK 0x00000400
3338 #define A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT 10
A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val)3339 static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val)
3340 {
3341 return ((val) << A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT) & A6XX_RB_MRT_BUF_INFO_UNK10__MASK;
3342 }
3343 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
3344 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)3345 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3346 {
3347 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
3348 }
3349
REG_A6XX_RB_MRT_PITCH(uint32_t i0)3350 static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }
3351 #define A6XX_RB_MRT_PITCH__MASK 0x0000ffff
3352 #define A6XX_RB_MRT_PITCH__SHIFT 0
A6XX_RB_MRT_PITCH(uint32_t val)3353 static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val)
3354 {
3355 return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK;
3356 }
3357
REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0)3358 static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }
3359 #define A6XX_RB_MRT_ARRAY_PITCH__MASK 0x1fffffff
3360 #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0
A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)3361 static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)
3362 {
3363 return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
3364 }
3365
REG_A6XX_RB_MRT_BASE(uint32_t i0)3366 static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3367 #define A6XX_RB_MRT_BASE__MASK 0xffffffff
3368 #define A6XX_RB_MRT_BASE__SHIFT 0
A6XX_RB_MRT_BASE(uint32_t val)3369 static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val)
3370 {
3371 return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK;
3372 }
3373
REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0)3374 static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }
3375 #define A6XX_RB_MRT_BASE_GMEM__MASK 0xfffff000
3376 #define A6XX_RB_MRT_BASE_GMEM__SHIFT 12
A6XX_RB_MRT_BASE_GMEM(uint32_t val)3377 static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val)
3378 {
3379 return ((val >> 12) << A6XX_RB_MRT_BASE_GMEM__SHIFT) & A6XX_RB_MRT_BASE_GMEM__MASK;
3380 }
3381
3382 #define REG_A6XX_RB_BLEND_RED_F32 0x00008860
3383 #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff
3384 #define A6XX_RB_BLEND_RED_F32__SHIFT 0
A6XX_RB_BLEND_RED_F32(float val)3385 static inline uint32_t A6XX_RB_BLEND_RED_F32(float val)
3386 {
3387 return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK;
3388 }
3389
3390 #define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861
3391 #define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
3392 #define A6XX_RB_BLEND_GREEN_F32__SHIFT 0
A6XX_RB_BLEND_GREEN_F32(float val)3393 static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val)
3394 {
3395 return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK;
3396 }
3397
3398 #define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862
3399 #define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
3400 #define A6XX_RB_BLEND_BLUE_F32__SHIFT 0
A6XX_RB_BLEND_BLUE_F32(float val)3401 static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val)
3402 {
3403 return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK;
3404 }
3405
3406 #define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863
3407 #define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
3408 #define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0
A6XX_RB_BLEND_ALPHA_F32(float val)3409 static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val)
3410 {
3411 return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK;
3412 }
3413
3414 #define REG_A6XX_RB_ALPHA_CONTROL 0x00008864
3415 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
3416 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)3417 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
3418 {
3419 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
3420 }
3421 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
3422 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
3423 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)3424 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
3425 {
3426 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
3427 }
3428
3429 #define REG_A6XX_RB_BLEND_CNTL 0x00008865
3430 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
3431 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)3432 static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
3433 {
3434 return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
3435 }
3436 #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
3437 #define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200
3438 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
3439 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE 0x00000800
3440 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
3441 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)3442 static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
3443 {
3444 return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
3445 }
3446
3447 #define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870
3448 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003
3449 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0
A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)3450 static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
3451 {
3452 return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK;
3453 }
3454
3455 #define REG_A6XX_RB_DEPTH_CNTL 0x00008871
3456 #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001
3457 #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
3458 #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
3459 #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)3460 static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
3461 {
3462 return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
3463 }
3464 #define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE 0x00000020
3465 #define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE 0x00000040
3466 #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080
3467
3468 #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872
3469 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
3470 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)3471 static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
3472 {
3473 return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
3474 }
3475 #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018
3476 #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3
A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val)3477 static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
3478 {
3479 return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK;
3480 }
3481
3482 #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873
3483 #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0x00003fff
3484 #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)3485 static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
3486 {
3487 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK;
3488 }
3489
3490 #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874
3491 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0x0fffffff
3492 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)3493 static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
3494 {
3495 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
3496 }
3497
3498 #define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875
3499 #define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff
3500 #define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0
A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val)3501 static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val)
3502 {
3503 return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK;
3504 }
3505
3506 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877
3507 #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK 0xfffff000
3508 #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT 12
A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val)3509 static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val)
3510 {
3511 return ((val >> 12) << A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK;
3512 }
3513
3514 #define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878
3515 #define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff
3516 #define A6XX_RB_Z_BOUNDS_MIN__SHIFT 0
A6XX_RB_Z_BOUNDS_MIN(float val)3517 static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val)
3518 {
3519 return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK;
3520 }
3521
3522 #define REG_A6XX_RB_Z_BOUNDS_MAX 0x00008879
3523 #define A6XX_RB_Z_BOUNDS_MAX__MASK 0xffffffff
3524 #define A6XX_RB_Z_BOUNDS_MAX__SHIFT 0
A6XX_RB_Z_BOUNDS_MAX(float val)3525 static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val)
3526 {
3527 return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK;
3528 }
3529
3530 #define REG_A6XX_RB_STENCIL_CONTROL 0x00008880
3531 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
3532 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
3533 #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
3534 #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
3535 #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)3536 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
3537 {
3538 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK;
3539 }
3540 #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
3541 #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)3542 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
3543 {
3544 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK;
3545 }
3546 #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
3547 #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)3548 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
3549 {
3550 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK;
3551 }
3552 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
3553 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)3554 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
3555 {
3556 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
3557 }
3558 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
3559 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)3560 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
3561 {
3562 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
3563 }
3564 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
3565 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)3566 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
3567 {
3568 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
3569 }
3570 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
3571 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)3572 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
3573 {
3574 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
3575 }
3576 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
3577 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)3578 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
3579 {
3580 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
3581 }
3582
3583 #define REG_A6XX_RB_STENCIL_INFO 0x00008881
3584 #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
3585 #define A6XX_RB_STENCIL_INFO_UNK1 0x00000002
3586
3587 #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882
3588 #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0x00000fff
3589 #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0
A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)3590 static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)
3591 {
3592 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK;
3593 }
3594
3595 #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883
3596 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0x00ffffff
3597 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0
A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)3598 static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
3599 {
3600 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
3601 }
3602
3603 #define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884
3604 #define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff
3605 #define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0
A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val)3606 static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val)
3607 {
3608 return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK;
3609 }
3610
3611 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886
3612 #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK 0xfffff000
3613 #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT 12
A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val)3614 static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val)
3615 {
3616 return ((val >> 12) << A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK;
3617 }
3618
3619 #define REG_A6XX_RB_STENCILREF 0x00008887
3620 #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff
3621 #define A6XX_RB_STENCILREF_REF__SHIFT 0
A6XX_RB_STENCILREF_REF(uint32_t val)3622 static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val)
3623 {
3624 return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK;
3625 }
3626 #define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00
3627 #define A6XX_RB_STENCILREF_BFREF__SHIFT 8
A6XX_RB_STENCILREF_BFREF(uint32_t val)3628 static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val)
3629 {
3630 return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK;
3631 }
3632
3633 #define REG_A6XX_RB_STENCILMASK 0x00008888
3634 #define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff
3635 #define A6XX_RB_STENCILMASK_MASK__SHIFT 0
A6XX_RB_STENCILMASK_MASK(uint32_t val)3636 static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val)
3637 {
3638 return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK;
3639 }
3640 #define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00
3641 #define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8
A6XX_RB_STENCILMASK_BFMASK(uint32_t val)3642 static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val)
3643 {
3644 return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK;
3645 }
3646
3647 #define REG_A6XX_RB_STENCILWRMASK 0x00008889
3648 #define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff
3649 #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0
A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val)3650 static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val)
3651 {
3652 return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK;
3653 }
3654 #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00
3655 #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8
A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val)3656 static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val)
3657 {
3658 return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK;
3659 }
3660
3661 #define REG_A6XX_RB_WINDOW_OFFSET 0x00008890
3662 #define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00003fff
3663 #define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0
A6XX_RB_WINDOW_OFFSET_X(uint32_t val)3664 static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val)
3665 {
3666 return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK;
3667 }
3668 #define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x3fff0000
3669 #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16
A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)3670 static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)
3671 {
3672 return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK;
3673 }
3674
3675 #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891
3676 #define A6XX_RB_SAMPLE_COUNT_CONTROL_UNK0 0x00000001
3677 #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
3678
3679 #define REG_A6XX_RB_LRZ_CNTL 0x00008898
3680 #define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001
3681
3682 #define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0
3683 #define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff
3684 #define A6XX_RB_Z_CLAMP_MIN__SHIFT 0
A6XX_RB_Z_CLAMP_MIN(float val)3685 static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val)
3686 {
3687 return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK;
3688 }
3689
3690 #define REG_A6XX_RB_Z_CLAMP_MAX 0x000088c1
3691 #define A6XX_RB_Z_CLAMP_MAX__MASK 0xffffffff
3692 #define A6XX_RB_Z_CLAMP_MAX__SHIFT 0
A6XX_RB_Z_CLAMP_MAX(float val)3693 static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val)
3694 {
3695 return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK;
3696 }
3697
3698 #define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0
3699 #define A6XX_RB_UNKNOWN_88D0_UNK0__MASK 0x00001fff
3700 #define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT 0
A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val)3701 static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val)
3702 {
3703 return ((val) << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK;
3704 }
3705 #define A6XX_RB_UNKNOWN_88D0_UNK16__MASK 0x07ff0000
3706 #define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT 16
A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val)3707 static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val)
3708 {
3709 return ((val) << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK;
3710 }
3711
3712 #define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1
3713 #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00003fff
3714 #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0
A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val)3715 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val)
3716 {
3717 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK;
3718 }
3719 #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x3fff0000
3720 #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16
A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val)3721 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val)
3722 {
3723 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK;
3724 }
3725
3726 #define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2
3727 #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00003fff
3728 #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0
A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val)3729 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val)
3730 {
3731 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK;
3732 }
3733 #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x3fff0000
3734 #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16
A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)3735 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)
3736 {
3737 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK;
3738 }
3739
3740 #define REG_A6XX_RB_BIN_CONTROL2 0x000088d3
3741 #define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x0000003f
3742 #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0
A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)3743 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)
3744 {
3745 return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK;
3746 }
3747 #define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x00007f00
3748 #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8
A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)3749 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)
3750 {
3751 return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK;
3752 }
3753
3754 #define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4
3755 #define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00003fff
3756 #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0
A6XX_RB_WINDOW_OFFSET2_X(uint32_t val)3757 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val)
3758 {
3759 return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK;
3760 }
3761 #define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x3fff0000
3762 #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16
A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val)3763 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val)
3764 {
3765 return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK;
3766 }
3767
3768 #define REG_A6XX_RB_MSAA_CNTL 0x000088d5
3769 #define A6XX_RB_MSAA_CNTL_SAMPLES__MASK 0x00000018
3770 #define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT 3
A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)3771 static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3772 {
3773 return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK;
3774 }
3775
3776 #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6
3777 #define A6XX_RB_BLIT_BASE_GMEM__MASK 0xfffff000
3778 #define A6XX_RB_BLIT_BASE_GMEM__SHIFT 12
A6XX_RB_BLIT_BASE_GMEM(uint32_t val)3779 static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val)
3780 {
3781 return ((val >> 12) << A6XX_RB_BLIT_BASE_GMEM__SHIFT) & A6XX_RB_BLIT_BASE_GMEM__MASK;
3782 }
3783
3784 #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7
3785 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003
3786 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0
A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)3787 static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
3788 {
3789 return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK;
3790 }
3791 #define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004
3792 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018
3793 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3
A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)3794 static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
3795 {
3796 return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK;
3797 }
3798 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060
3799 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5
A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)3800 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3801 {
3802 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK;
3803 }
3804 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80
3805 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7
A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val)3806 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
3807 {
3808 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK;
3809 }
3810 #define A6XX_RB_BLIT_DST_INFO_UNK15 0x00008000
3811
3812 #define REG_A6XX_RB_BLIT_DST 0x000088d8
3813 #define A6XX_RB_BLIT_DST__MASK 0xffffffff
3814 #define A6XX_RB_BLIT_DST__SHIFT 0
A6XX_RB_BLIT_DST(uint32_t val)3815 static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val)
3816 {
3817 return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK;
3818 }
3819
3820 #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da
3821 #define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff
3822 #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0
A6XX_RB_BLIT_DST_PITCH(uint32_t val)3823 static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val)
3824 {
3825 return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK;
3826 }
3827
3828 #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db
3829 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0x1fffffff
3830 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)3831 static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
3832 {
3833 return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
3834 }
3835
3836 #define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc
3837 #define A6XX_RB_BLIT_FLAG_DST__MASK 0xffffffff
3838 #define A6XX_RB_BLIT_FLAG_DST__SHIFT 0
A6XX_RB_BLIT_FLAG_DST(uint32_t val)3839 static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val)
3840 {
3841 return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK;
3842 }
3843
3844 #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de
3845 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff
3846 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0
A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)3847 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)
3848 {
3849 return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK;
3850 }
3851 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800
3852 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11
A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val)3853 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val)
3854 {
3855 return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK;
3856 }
3857
3858 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df
3859
3860 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0
3861
3862 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1
3863
3864 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2
3865
3866 #define REG_A6XX_RB_BLIT_INFO 0x000088e3
3867 #define A6XX_RB_BLIT_INFO_UNK0 0x00000001
3868 #define A6XX_RB_BLIT_INFO_GMEM 0x00000002
3869 #define A6XX_RB_BLIT_INFO_SAMPLE_0 0x00000004
3870 #define A6XX_RB_BLIT_INFO_DEPTH 0x00000008
3871 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0
3872 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4
A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)3873 static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)
3874 {
3875 return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK;
3876 }
3877 #define A6XX_RB_BLIT_INFO_UNK8__MASK 0x00000300
3878 #define A6XX_RB_BLIT_INFO_UNK8__SHIFT 8
A6XX_RB_BLIT_INFO_UNK8(uint32_t val)3879 static inline uint32_t A6XX_RB_BLIT_INFO_UNK8(uint32_t val)
3880 {
3881 return ((val) << A6XX_RB_BLIT_INFO_UNK8__SHIFT) & A6XX_RB_BLIT_INFO_UNK8__MASK;
3882 }
3883 #define A6XX_RB_BLIT_INFO_UNK12__MASK 0x0000f000
3884 #define A6XX_RB_BLIT_INFO_UNK12__SHIFT 12
A6XX_RB_BLIT_INFO_UNK12(uint32_t val)3885 static inline uint32_t A6XX_RB_BLIT_INFO_UNK12(uint32_t val)
3886 {
3887 return ((val) << A6XX_RB_BLIT_INFO_UNK12__SHIFT) & A6XX_RB_BLIT_INFO_UNK12__MASK;
3888 }
3889
3890 #define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0
3891
3892 #define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1
3893 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK 0xffffffff
3894 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT 0
A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val)3895 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val)
3896 {
3897 return ((val) << A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK;
3898 }
3899
3900 #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH 0x000088f3
3901 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
3902 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val)3903 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
3904 {
3905 return ((val >> 6) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK;
3906 }
3907 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x00fff800
3908 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)3909 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3910 {
3911 return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3912 }
3913
3914 #define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4
3915
3916 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900
3917 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff
3918 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0
A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val)3919 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val)
3920 {
3921 return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK;
3922 }
3923
3924 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902
3925 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x0000007f
3926 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val)3927 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
3928 {
3929 return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK;
3930 }
3931 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK 0x00000700
3932 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT 8
A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val)3933 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val)
3934 {
3935 return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK;
3936 }
3937 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x0ffff800
3938 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)3939 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3940 {
3941 return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3942 }
3943
REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0)3944 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3945
REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0)3946 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3947 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff
3948 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0
A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val)3949 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val)
3950 {
3951 return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK;
3952 }
3953
REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0)3954 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; }
3955 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
3956 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)3957 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
3958 {
3959 return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
3960 }
3961 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800
3962 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)3963 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3964 {
3965 return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3966 }
3967
3968 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927
3969 #define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff
3970 #define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0
A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val)3971 static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val)
3972 {
3973 return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK;
3974 }
3975
3976 #define REG_A6XX_RB_UNKNOWN_8A00 0x00008a00
3977
3978 #define REG_A6XX_RB_UNKNOWN_8A10 0x00008a10
3979
3980 #define REG_A6XX_RB_UNKNOWN_8A20 0x00008a20
3981
3982 #define REG_A6XX_RB_UNKNOWN_8A30 0x00008a30
3983
3984 #define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00
3985 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000007
3986 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0
A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)3987 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
3988 {
3989 return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK;
3990 }
3991 #define A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN 0x00000008
3992 #define A6XX_RB_2D_BLIT_CNTL_UNK4__MASK 0x00000070
3993 #define A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT 4
A6XX_RB_2D_BLIT_CNTL_UNK4(uint32_t val)3994 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK4(uint32_t val)
3995 {
3996 return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK4__MASK;
3997 }
3998 #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000080
3999 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
4000 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)4001 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
4002 {
4003 return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
4004 }
4005 #define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000
4006 #define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK 0x00060000
4007 #define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT 17
A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val)4008 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val)
4009 {
4010 return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK;
4011 }
4012 #define A6XX_RB_2D_BLIT_CNTL_D24S8 0x00080000
4013 #define A6XX_RB_2D_BLIT_CNTL_MASK__MASK 0x00f00000
4014 #define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT 20
A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val)4015 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val)
4016 {
4017 return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK;
4018 }
4019 #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000
4020 #define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24
A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)4021 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
4022 {
4023 return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK;
4024 }
4025 #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000
4026 #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29
A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val)4027 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
4028 {
4029 return ((val) << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK;
4030 }
4031
4032 #define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01
4033
4034 #define REG_A6XX_RB_2D_DST_INFO 0x00008c17
4035 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
4036 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val)4037 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
4038 {
4039 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
4040 }
4041 #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300
4042 #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8
A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)4043 static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
4044 {
4045 return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK;
4046 }
4047 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
4048 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)4049 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4050 {
4051 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
4052 }
4053 #define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000
4054 #define A6XX_RB_2D_DST_INFO_SRGB 0x00002000
4055 #define A6XX_RB_2D_DST_INFO_SAMPLES__MASK 0x0000c000
4056 #define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT 14
A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)4057 static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
4058 {
4059 return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK;
4060 }
4061 #define A6XX_RB_2D_DST_INFO_FILTER 0x00010000
4062 #define A6XX_RB_2D_DST_INFO_UNK17 0x00020000
4063 #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000
4064 #define A6XX_RB_2D_DST_INFO_UNK19 0x00080000
4065 #define A6XX_RB_2D_DST_INFO_UNK20 0x00100000
4066 #define A6XX_RB_2D_DST_INFO_UNK21 0x00200000
4067 #define A6XX_RB_2D_DST_INFO_UNK22 0x00400000
4068 #define A6XX_RB_2D_DST_INFO_UNK23__MASK 0x07800000
4069 #define A6XX_RB_2D_DST_INFO_UNK23__SHIFT 23
A6XX_RB_2D_DST_INFO_UNK23(uint32_t val)4070 static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val)
4071 {
4072 return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK;
4073 }
4074 #define A6XX_RB_2D_DST_INFO_UNK28 0x10000000
4075
4076 #define REG_A6XX_RB_2D_DST 0x00008c18
4077 #define A6XX_RB_2D_DST__MASK 0xffffffff
4078 #define A6XX_RB_2D_DST__SHIFT 0
A6XX_RB_2D_DST(uint32_t val)4079 static inline uint32_t A6XX_RB_2D_DST(uint32_t val)
4080 {
4081 return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK;
4082 }
4083
4084 #define REG_A6XX_RB_2D_DST_PITCH 0x00008c1a
4085 #define A6XX_RB_2D_DST_PITCH__MASK 0x0000ffff
4086 #define A6XX_RB_2D_DST_PITCH__SHIFT 0
A6XX_RB_2D_DST_PITCH(uint32_t val)4087 static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val)
4088 {
4089 return ((val >> 6) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK;
4090 }
4091
4092 #define REG_A6XX_RB_2D_DST_PLANE1 0x00008c1b
4093 #define A6XX_RB_2D_DST_PLANE1__MASK 0xffffffff
4094 #define A6XX_RB_2D_DST_PLANE1__SHIFT 0
A6XX_RB_2D_DST_PLANE1(uint32_t val)4095 static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val)
4096 {
4097 return ((val) << A6XX_RB_2D_DST_PLANE1__SHIFT) & A6XX_RB_2D_DST_PLANE1__MASK;
4098 }
4099
4100 #define REG_A6XX_RB_2D_DST_PLANE_PITCH 0x00008c1d
4101 #define A6XX_RB_2D_DST_PLANE_PITCH__MASK 0x0000ffff
4102 #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT 0
A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val)4103 static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val)
4104 {
4105 return ((val >> 6) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK;
4106 }
4107
4108 #define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e
4109 #define A6XX_RB_2D_DST_PLANE2__MASK 0xffffffff
4110 #define A6XX_RB_2D_DST_PLANE2__SHIFT 0
A6XX_RB_2D_DST_PLANE2(uint32_t val)4111 static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val)
4112 {
4113 return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK;
4114 }
4115
4116 #define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20
4117 #define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff
4118 #define A6XX_RB_2D_DST_FLAGS__SHIFT 0
A6XX_RB_2D_DST_FLAGS(uint32_t val)4119 static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val)
4120 {
4121 return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK;
4122 }
4123
4124 #define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22
4125 #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK 0x000000ff
4126 #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0
A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)4127 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
4128 {
4129 return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK;
4130 }
4131
4132 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE 0x00008c23
4133 #define A6XX_RB_2D_DST_FLAGS_PLANE__MASK 0xffffffff
4134 #define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT 0
A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val)4135 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val)
4136 {
4137 return ((val) << A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE__MASK;
4138 }
4139
4140 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH 0x00008c25
4141 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK 0x000000ff
4142 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT 0
A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val)4143 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val)
4144 {
4145 return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK;
4146 }
4147
4148 #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c
4149
4150 #define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d
4151
4152 #define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e
4153
4154 #define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f
4155
4156 #define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01
4157
4158 #define REG_A6XX_RB_UNKNOWN_8E04 0x00008e04
4159
4160 #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05
4161
4162 #define REG_A6XX_RB_CCU_CNTL 0x00008e07
4163 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK 0xff800000
4164 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT 23
A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val)4165 static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val)
4166 {
4167 return ((val >> 12) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK;
4168 }
4169 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK 0x001ff000
4170 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT 12
A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val)4171 static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val)
4172 {
4173 return ((val >> 12) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK;
4174 }
4175 #define A6XX_RB_CCU_CNTL_GMEM 0x00400000
4176 #define A6XX_RB_CCU_CNTL_UNK2 0x00000004
4177
4178 #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08
4179 #define A6XX_RB_NC_MODE_CNTL_MODE 0x00000001
4180 #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006
4181 #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT 1
A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val)4182 static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
4183 {
4184 return ((val) << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK;
4185 }
4186 #define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008
4187 #define A6XX_RB_NC_MODE_CNTL_AMSBC 0x00000010
4188 #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000400
4189 #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT 10
A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val)4190 static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
4191 {
4192 return ((val) << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK;
4193 }
4194 #define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR 0x00000800
4195 #define A6XX_RB_NC_MODE_CNTL_UNK12__MASK 0x00003000
4196 #define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT 12
A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val)4197 static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val)
4198 {
4199 return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK;
4200 }
4201
REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0)4202 static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; }
4203
REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0)4204 static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; }
4205
4206 #define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28
4207
REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0)4208 static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; }
4209
4210 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b
4211
4212 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d
4213
4214 #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50
4215
4216 #define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51
4217 #define A6XX_RB_UNKNOWN_8E51__MASK 0xffffffff
4218 #define A6XX_RB_UNKNOWN_8E51__SHIFT 0
A6XX_RB_UNKNOWN_8E51(uint32_t val)4219 static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val)
4220 {
4221 return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK;
4222 }
4223
4224 #define REG_A6XX_VPC_GS_PARAM 0x00009100
4225 #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK 0x000000ff
4226 #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT 0
A6XX_VPC_GS_PARAM_LINELENGTHLOC(uint32_t val)4227 static inline uint32_t A6XX_VPC_GS_PARAM_LINELENGTHLOC(uint32_t val)
4228 {
4229 return ((val) << A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT) & A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK;
4230 }
4231
4232 #define REG_A6XX_VPC_VS_CLIP_CNTL 0x00009101
4233 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
4234 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT 0
A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val)4235 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4236 {
4237 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK;
4238 }
4239 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
4240 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)4241 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4242 {
4243 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4244 }
4245 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
4246 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)4247 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4248 {
4249 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4250 }
4251
4252 #define REG_A6XX_VPC_GS_CLIP_CNTL 0x00009102
4253 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
4254 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT 0
A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val)4255 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4256 {
4257 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK;
4258 }
4259 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
4260 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)4261 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4262 {
4263 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4264 }
4265 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
4266 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)4267 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4268 {
4269 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4270 }
4271
4272 #define REG_A6XX_VPC_DS_CLIP_CNTL 0x00009103
4273 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
4274 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT 0
A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val)4275 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4276 {
4277 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK;
4278 }
4279 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
4280 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)4281 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4282 {
4283 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4284 }
4285 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
4286 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)4287 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4288 {
4289 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4290 }
4291
4292 #define REG_A6XX_VPC_VS_LAYER_CNTL 0x00009104
4293 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
4294 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT 0
A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val)4295 static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val)
4296 {
4297 return ((val) << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK;
4298 }
4299 #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00
4300 #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT 8
A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val)4301 static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val)
4302 {
4303 return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK;
4304 }
4305
4306 #define REG_A6XX_VPC_GS_LAYER_CNTL 0x00009105
4307 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
4308 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT 0
A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val)4309 static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val)
4310 {
4311 return ((val) << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK;
4312 }
4313 #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00
4314 #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT 8
A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val)4315 static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val)
4316 {
4317 return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK;
4318 }
4319
4320 #define REG_A6XX_VPC_DS_LAYER_CNTL 0x00009106
4321 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
4322 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT 0
A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val)4323 static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val)
4324 {
4325 return ((val) << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK;
4326 }
4327 #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00
4328 #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT 8
A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val)4329 static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val)
4330 {
4331 return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK;
4332 }
4333
4334 #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107
4335 #define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001
4336 #define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004
4337
4338 #define REG_A6XX_VPC_POLYGON_MODE 0x00009108
4339 #define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003
4340 #define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0
A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)4341 static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
4342 {
4343 return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK;
4344 }
4345
REG_A6XX_VPC_VARYING_INTERP(uint32_t i0)4346 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }
4347
REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0)4348 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; }
4349
REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0)4350 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; }
4351
REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0)4352 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; }
4353
4354 #define REG_A6XX_VPC_UNKNOWN_9210 0x00009210
4355
4356 #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211
4357
REG_A6XX_VPC_VAR(uint32_t i0)4358 static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4359
REG_A6XX_VPC_VAR_DISABLE(uint32_t i0)4360 static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4361
4362 #define REG_A6XX_VPC_SO_CNTL 0x00009216
4363 #define A6XX_VPC_SO_CNTL_ADDR__MASK 0x000000ff
4364 #define A6XX_VPC_SO_CNTL_ADDR__SHIFT 0
A6XX_VPC_SO_CNTL_ADDR(uint32_t val)4365 static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val)
4366 {
4367 return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK;
4368 }
4369 #define A6XX_VPC_SO_CNTL_RESET 0x00010000
4370
4371 #define REG_A6XX_VPC_SO_PROG 0x00009217
4372 #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
4373 #define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0
A6XX_VPC_SO_PROG_A_BUF(uint32_t val)4374 static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val)
4375 {
4376 return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK;
4377 }
4378 #define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
4379 #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2
A6XX_VPC_SO_PROG_A_OFF(uint32_t val)4380 static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val)
4381 {
4382 return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK;
4383 }
4384 #define A6XX_VPC_SO_PROG_A_EN 0x00000800
4385 #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
4386 #define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12
A6XX_VPC_SO_PROG_B_BUF(uint32_t val)4387 static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val)
4388 {
4389 return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK;
4390 }
4391 #define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
4392 #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14
A6XX_VPC_SO_PROG_B_OFF(uint32_t val)4393 static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val)
4394 {
4395 return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK;
4396 }
4397 #define A6XX_VPC_SO_PROG_B_EN 0x00800000
4398
4399 #define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218
4400 #define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff
4401 #define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0
A6XX_VPC_SO_STREAM_COUNTS(uint32_t val)4402 static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val)
4403 {
4404 return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK;
4405 }
4406
REG_A6XX_VPC_SO(uint32_t i0)4407 static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4408
REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0)4409 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4410 #define A6XX_VPC_SO_BUFFER_BASE__MASK 0xffffffff
4411 #define A6XX_VPC_SO_BUFFER_BASE__SHIFT 0
A6XX_VPC_SO_BUFFER_BASE(uint32_t val)4412 static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val)
4413 {
4414 return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK;
4415 }
4416
REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0)4417 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
4418 #define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc
4419 #define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2
A6XX_VPC_SO_BUFFER_SIZE(uint32_t val)4420 static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val)
4421 {
4422 return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK;
4423 }
4424
REG_A6XX_VPC_SO_NCOMP(uint32_t i0)4425 static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; }
4426
REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0)4427 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }
4428 #define A6XX_VPC_SO_BUFFER_OFFSET__MASK 0xfffffffc
4429 #define A6XX_VPC_SO_BUFFER_OFFSET__SHIFT 2
A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val)4430 static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val)
4431 {
4432 return ((val >> 2) << A6XX_VPC_SO_BUFFER_OFFSET__SHIFT) & A6XX_VPC_SO_BUFFER_OFFSET__MASK;
4433 }
4434
REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0)4435 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; }
4436 #define A6XX_VPC_SO_FLUSH_BASE__MASK 0xffffffff
4437 #define A6XX_VPC_SO_FLUSH_BASE__SHIFT 0
A6XX_VPC_SO_FLUSH_BASE(uint32_t val)4438 static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val)
4439 {
4440 return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK;
4441 }
4442
4443 #define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236
4444 #define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001
4445
4446 #define REG_A6XX_VPC_UNKNOWN_9300 0x00009300
4447
4448 #define REG_A6XX_VPC_VS_PACK 0x00009301
4449 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
4450 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT 0
A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val)4451 static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val)
4452 {
4453 return ((val) << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK;
4454 }
4455 #define A6XX_VPC_VS_PACK_POSITIONLOC__MASK 0x0000ff00
4456 #define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT 8
A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val)4457 static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val)
4458 {
4459 return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK;
4460 }
4461 #define A6XX_VPC_VS_PACK_PSIZELOC__MASK 0x00ff0000
4462 #define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT 16
A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val)4463 static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val)
4464 {
4465 return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK;
4466 }
4467 #define A6XX_VPC_VS_PACK_EXTRAPOS__MASK 0x0f000000
4468 #define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT 24
A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val)4469 static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val)
4470 {
4471 return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK;
4472 }
4473
4474 #define REG_A6XX_VPC_GS_PACK 0x00009302
4475 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
4476 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT 0
A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val)4477 static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val)
4478 {
4479 return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK;
4480 }
4481 #define A6XX_VPC_GS_PACK_POSITIONLOC__MASK 0x0000ff00
4482 #define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT 8
A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val)4483 static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val)
4484 {
4485 return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK;
4486 }
4487 #define A6XX_VPC_GS_PACK_PSIZELOC__MASK 0x00ff0000
4488 #define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT 16
A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val)4489 static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val)
4490 {
4491 return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK;
4492 }
4493 #define A6XX_VPC_GS_PACK_EXTRAPOS__MASK 0x0f000000
4494 #define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT 24
A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val)4495 static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val)
4496 {
4497 return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK;
4498 }
4499
4500 #define REG_A6XX_VPC_DS_PACK 0x00009303
4501 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
4502 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT 0
A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val)4503 static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val)
4504 {
4505 return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK;
4506 }
4507 #define A6XX_VPC_DS_PACK_POSITIONLOC__MASK 0x0000ff00
4508 #define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT 8
A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val)4509 static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val)
4510 {
4511 return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK;
4512 }
4513 #define A6XX_VPC_DS_PACK_PSIZELOC__MASK 0x00ff0000
4514 #define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT 16
A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val)4515 static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val)
4516 {
4517 return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK;
4518 }
4519 #define A6XX_VPC_DS_PACK_EXTRAPOS__MASK 0x0f000000
4520 #define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT 24
A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val)4521 static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val)
4522 {
4523 return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK;
4524 }
4525
4526 #define REG_A6XX_VPC_CNTL_0 0x00009304
4527 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff
4528 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0
A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)4529 static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
4530 {
4531 return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK;
4532 }
4533 #define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK 0x0000ff00
4534 #define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT 8
A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val)4535 static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val)
4536 {
4537 return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK;
4538 }
4539 #define A6XX_VPC_CNTL_0_VARYING 0x00010000
4540 #define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK 0xff000000
4541 #define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT 24
A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val)4542 static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val)
4543 {
4544 return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK;
4545 }
4546
4547 #define REG_A6XX_VPC_SO_STREAM_CNTL 0x00009305
4548 #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK 0x00000007
4549 #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT 0
A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val)4550 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val)
4551 {
4552 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK;
4553 }
4554 #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK 0x00000038
4555 #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT 3
A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val)4556 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val)
4557 {
4558 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK;
4559 }
4560 #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK 0x000001c0
4561 #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT 6
A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val)4562 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val)
4563 {
4564 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK;
4565 }
4566 #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK 0x00000e00
4567 #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT 9
A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val)4568 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val)
4569 {
4570 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK;
4571 }
4572 #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000
4573 #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15
A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val)4574 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val)
4575 {
4576 return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK;
4577 }
4578
4579 #define REG_A6XX_VPC_SO_DISABLE 0x00009306
4580 #define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001
4581
4582 #define REG_A6XX_VPC_UNKNOWN_9600 0x00009600
4583
4584 #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601
4585
4586 #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602
4587
4588 #define REG_A6XX_VPC_UNKNOWN_9603 0x00009603
4589
REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0)4590 static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; }
4591
4592 #define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800
4593
4594 #define REG_A6XX_PC_HS_INPUT_SIZE 0x00009801
4595 #define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK 0x000007ff
4596 #define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT 0
A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val)4597 static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val)
4598 {
4599 return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK;
4600 }
4601 #define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK 0x00002000
4602 #define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT 13
A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val)4603 static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val)
4604 {
4605 return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK;
4606 }
4607
4608 #define REG_A6XX_PC_TESS_CNTL 0x00009802
4609 #define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003
4610 #define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0
A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val)4611 static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val)
4612 {
4613 return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK;
4614 }
4615 #define A6XX_PC_TESS_CNTL_OUTPUT__MASK 0x0000000c
4616 #define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT 2
A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val)4617 static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val)
4618 {
4619 return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK;
4620 }
4621
4622 #define REG_A6XX_PC_RESTART_INDEX 0x00009803
4623
4624 #define REG_A6XX_PC_MODE_CNTL 0x00009804
4625
4626 #define REG_A6XX_PC_POWER_CNTL 0x00009805
4627
4628 #define REG_A6XX_PC_PRIMID_PASSTHRU 0x00009806
4629
4630 #define REG_A6XX_PC_SO_STREAM_CNTL 0x00009808
4631 #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE 0x00008000
4632
4633 #define REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL 0x0000980a
4634 #define A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001
4635
4636 #define REG_A6XX_PC_DRAW_CMD 0x00009840
4637 #define A6XX_PC_DRAW_CMD_STATE_ID__MASK 0x000000ff
4638 #define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT 0
A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val)4639 static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val)
4640 {
4641 return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK;
4642 }
4643
4644 #define REG_A6XX_PC_DISPATCH_CMD 0x00009841
4645 #define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK 0x000000ff
4646 #define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT 0
A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val)4647 static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val)
4648 {
4649 return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK;
4650 }
4651
4652 #define REG_A6XX_PC_EVENT_CMD 0x00009842
4653 #define A6XX_PC_EVENT_CMD_STATE_ID__MASK 0x00ff0000
4654 #define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT 16
A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val)4655 static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val)
4656 {
4657 return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK;
4658 }
4659 #define A6XX_PC_EVENT_CMD_EVENT__MASK 0x0000007f
4660 #define A6XX_PC_EVENT_CMD_EVENT__SHIFT 0
A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val)4661 static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val)
4662 {
4663 return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK;
4664 }
4665
4666 #define REG_A6XX_PC_MARKER 0x00009880
4667
4668 #define REG_A6XX_PC_POLYGON_MODE 0x00009981
4669 #define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003
4670 #define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0
A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)4671 static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
4672 {
4673 return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK;
4674 }
4675
4676 #define REG_A6XX_PC_RASTER_CNTL 0x00009980
4677 #define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003
4678 #define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0
A6XX_PC_RASTER_CNTL_STREAM(uint32_t val)4679 static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val)
4680 {
4681 return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK;
4682 }
4683 #define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004
4684
4685 #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00
4686 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
4687 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002
4688 #define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN 0x00000004
4689 #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008
4690
4691 #define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01
4692 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
4693 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)4694 static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
4695 {
4696 return ((val) << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK;
4697 }
4698 #define A6XX_PC_VS_OUT_CNTL_PSIZE 0x00000100
4699 #define A6XX_PC_VS_OUT_CNTL_LAYER 0x00000200
4700 #define A6XX_PC_VS_OUT_CNTL_VIEW 0x00000400
4701 #define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID 0x00000800
4702 #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
4703 #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT 16
A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val)4704 static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val)
4705 {
4706 return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK;
4707 }
4708
4709 #define REG_A6XX_PC_GS_OUT_CNTL 0x00009b02
4710 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
4711 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)4712 static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
4713 {
4714 return ((val) << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK;
4715 }
4716 #define A6XX_PC_GS_OUT_CNTL_PSIZE 0x00000100
4717 #define A6XX_PC_GS_OUT_CNTL_LAYER 0x00000200
4718 #define A6XX_PC_GS_OUT_CNTL_VIEW 0x00000400
4719 #define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID 0x00000800
4720 #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
4721 #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT 16
A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val)4722 static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val)
4723 {
4724 return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK;
4725 }
4726
4727 #define REG_A6XX_PC_HS_OUT_CNTL 0x00009b03
4728 #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
4729 #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)4730 static inline uint32_t A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
4731 {
4732 return ((val) << A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK;
4733 }
4734 #define A6XX_PC_HS_OUT_CNTL_PSIZE 0x00000100
4735 #define A6XX_PC_HS_OUT_CNTL_LAYER 0x00000200
4736 #define A6XX_PC_HS_OUT_CNTL_VIEW 0x00000400
4737 #define A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID 0x00000800
4738 #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
4739 #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT 16
A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val)4740 static inline uint32_t A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val)
4741 {
4742 return ((val) << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK;
4743 }
4744
4745 #define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04
4746 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
4747 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)4748 static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
4749 {
4750 return ((val) << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK;
4751 }
4752 #define A6XX_PC_DS_OUT_CNTL_PSIZE 0x00000100
4753 #define A6XX_PC_DS_OUT_CNTL_LAYER 0x00000200
4754 #define A6XX_PC_DS_OUT_CNTL_VIEW 0x00000400
4755 #define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID 0x00000800
4756 #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
4757 #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT 16
A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val)4758 static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val)
4759 {
4760 return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK;
4761 }
4762
4763 #define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05
4764 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff
4765 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0
A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val)4766 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val)
4767 {
4768 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK;
4769 }
4770 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00
4771 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10
A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val)4772 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val)
4773 {
4774 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK;
4775 }
4776 #define A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN 0x00008000
4777 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000
4778 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16
A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val)4779 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val)
4780 {
4781 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK;
4782 }
4783 #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK 0x00040000
4784 #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT 18
A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val)4785 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val)
4786 {
4787 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK;
4788 }
4789
4790 #define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06
4791 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff
4792 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT 0
A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val)4793 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val)
4794 {
4795 return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK;
4796 }
4797
4798 #define REG_A6XX_PC_MULTIVIEW_CNTL 0x00009b07
4799 #define A6XX_PC_MULTIVIEW_CNTL_ENABLE 0x00000001
4800 #define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
4801 #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
4802 #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT 2
A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val)4803 static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val)
4804 {
4805 return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK;
4806 }
4807
4808 #define REG_A6XX_PC_MULTIVIEW_MASK 0x00009b08
4809
4810 #define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00
4811 #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f
4812 #define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT 0
A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val)4813 static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
4814 {
4815 return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK;
4816 }
4817 #define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00
4818 #define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT 8
A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val)4819 static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val)
4820 {
4821 return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK;
4822 }
4823
4824 #define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00
4825
4826 #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01
4827
4828 #define REG_A6XX_PC_DRAW_INDX_BASE 0x00009e04
4829
4830 #define REG_A6XX_PC_DRAW_FIRST_INDX 0x00009e06
4831
4832 #define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07
4833
4834 #define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08
4835 #define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff
4836 #define A6XX_PC_TESSFACTOR_ADDR__SHIFT 0
A6XX_PC_TESSFACTOR_ADDR(uint32_t val)4837 static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val)
4838 {
4839 return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK;
4840 }
4841
4842 #define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b
4843 #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
4844 #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)4845 static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
4846 {
4847 return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK;
4848 }
4849 #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
4850 #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)4851 static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
4852 {
4853 return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK;
4854 }
4855 #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK 0x00000300
4856 #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT 8
A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)4857 static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
4858 {
4859 return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK;
4860 }
4861 #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000c00
4862 #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT 10
A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val)4863 static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val)
4864 {
4865 return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK;
4866 }
4867 #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK 0x00003000
4868 #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT 12
A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val)4869 static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val)
4870 {
4871 return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK;
4872 }
4873 #define A6XX_PC_DRAW_INITIATOR_GS_ENABLE 0x00010000
4874 #define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE 0x00020000
4875
4876 #define REG_A6XX_PC_DRAW_NUM_INSTANCES 0x00009e0c
4877
4878 #define REG_A6XX_PC_DRAW_NUM_INDICES 0x00009e0d
4879
4880 #define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11
4881 #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff
4882 #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0
A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val)4883 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val)
4884 {
4885 return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK;
4886 }
4887 #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK 0x003f0000
4888 #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT 16
A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val)4889 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val)
4890 {
4891 return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK;
4892 }
4893 #define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK 0x07c00000
4894 #define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT 22
A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val)4895 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val)
4896 {
4897 return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK;
4898 }
4899
4900 #define REG_A6XX_PC_BIN_PRIM_STRM 0x00009e12
4901 #define A6XX_PC_BIN_PRIM_STRM__MASK 0xffffffff
4902 #define A6XX_PC_BIN_PRIM_STRM__SHIFT 0
A6XX_PC_BIN_PRIM_STRM(uint32_t val)4903 static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val)
4904 {
4905 return ((val) << A6XX_PC_BIN_PRIM_STRM__SHIFT) & A6XX_PC_BIN_PRIM_STRM__MASK;
4906 }
4907
4908 #define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14
4909 #define A6XX_PC_BIN_DRAW_STRM__MASK 0xffffffff
4910 #define A6XX_PC_BIN_DRAW_STRM__SHIFT 0
A6XX_PC_BIN_DRAW_STRM(uint32_t val)4911 static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val)
4912 {
4913 return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK;
4914 }
4915
4916 #define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c
4917 #define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001
4918
REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0)4919 static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; }
4920
4921 #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72
4922
4923 #define REG_A6XX_VFD_CONTROL_0 0x0000a000
4924 #define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK 0x0000003f
4925 #define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT 0
A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val)4926 static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val)
4927 {
4928 return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK;
4929 }
4930 #define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK 0x00003f00
4931 #define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT 8
A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val)4932 static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val)
4933 {
4934 return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK;
4935 }
4936
4937 #define REG_A6XX_VFD_CONTROL_1 0x0000a001
4938 #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff
4939 #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0
A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)4940 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
4941 {
4942 return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK;
4943 }
4944 #define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
4945 #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val)4946 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
4947 {
4948 return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK;
4949 }
4950 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000
4951 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16
A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)4952 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
4953 {
4954 return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
4955 }
4956 #define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK 0xff000000
4957 #define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT 24
A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val)4958 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val)
4959 {
4960 return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK;
4961 }
4962
4963 #define REG_A6XX_VFD_CONTROL_2 0x0000a002
4964 #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK 0x000000ff
4965 #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT 0
A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(uint32_t val)4966 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(uint32_t val)
4967 {
4968 return ((val) << A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK;
4969 }
4970 #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00
4971 #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8
A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)4972 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)
4973 {
4974 return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK;
4975 }
4976
4977 #define REG_A6XX_VFD_CONTROL_3 0x0000a003
4978 #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK 0x000000ff
4979 #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT 0
A6XX_VFD_CONTROL_3_REGID_DSPRIMID(uint32_t val)4980 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPRIMID(uint32_t val)
4981 {
4982 return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK;
4983 }
4984 #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK 0x0000ff00
4985 #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT 8
A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(uint32_t val)4986 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(uint32_t val)
4987 {
4988 return ((val) << A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK;
4989 }
4990 #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
4991 #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)4992 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
4993 {
4994 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK;
4995 }
4996 #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
4997 #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)4998 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
4999 {
5000 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK;
5001 }
5002
5003 #define REG_A6XX_VFD_CONTROL_4 0x0000a004
5004 #define A6XX_VFD_CONTROL_4_UNK0__MASK 0x000000ff
5005 #define A6XX_VFD_CONTROL_4_UNK0__SHIFT 0
A6XX_VFD_CONTROL_4_UNK0(uint32_t val)5006 static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val)
5007 {
5008 return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK;
5009 }
5010
5011 #define REG_A6XX_VFD_CONTROL_5 0x0000a005
5012 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff
5013 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT 0
A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val)5014 static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val)
5015 {
5016 return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK;
5017 }
5018 #define A6XX_VFD_CONTROL_5_UNK8__MASK 0x0000ff00
5019 #define A6XX_VFD_CONTROL_5_UNK8__SHIFT 8
A6XX_VFD_CONTROL_5_UNK8(uint32_t val)5020 static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val)
5021 {
5022 return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK;
5023 }
5024
5025 #define REG_A6XX_VFD_CONTROL_6 0x0000a006
5026 #define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001
5027
5028 #define REG_A6XX_VFD_MODE_CNTL 0x0000a007
5029 #define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK 0x00000007
5030 #define A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT 0
A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val)5031 static inline uint32_t A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val)
5032 {
5033 return ((val) << A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT) & A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK;
5034 }
5035
5036 #define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008
5037 #define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001
5038 #define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
5039 #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
5040 #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT 2
A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val)5041 static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val)
5042 {
5043 return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK;
5044 }
5045
5046 #define REG_A6XX_VFD_ADD_OFFSET 0x0000a009
5047 #define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001
5048 #define A6XX_VFD_ADD_OFFSET_INSTANCE 0x00000002
5049
5050 #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e
5051
5052 #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f
5053
REG_A6XX_VFD_FETCH(uint32_t i0)5054 static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
5055
REG_A6XX_VFD_FETCH_BASE(uint32_t i0)5056 static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
5057 #define A6XX_VFD_FETCH_BASE__MASK 0xffffffff
5058 #define A6XX_VFD_FETCH_BASE__SHIFT 0
A6XX_VFD_FETCH_BASE(uint32_t val)5059 static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val)
5060 {
5061 return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK;
5062 }
5063
REG_A6XX_VFD_FETCH_SIZE(uint32_t i0)5064 static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
5065
REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0)5066 static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }
5067
REG_A6XX_VFD_DECODE(uint32_t i0)5068 static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
5069
REG_A6XX_VFD_DECODE_INSTR(uint32_t i0)5070 static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
5071 #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
5072 #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0
A6XX_VFD_DECODE_INSTR_IDX(uint32_t val)5073 static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val)
5074 {
5075 return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK;
5076 }
5077 #define A6XX_VFD_DECODE_INSTR_OFFSET__MASK 0x0001ffe0
5078 #define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT 5
A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val)5079 static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val)
5080 {
5081 return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK;
5082 }
5083 #define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
5084 #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000
5085 #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val)5086 static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val)
5087 {
5088 return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK;
5089 }
5090 #define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000
5091 #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28
A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)5092 static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
5093 {
5094 return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK;
5095 }
5096 #define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000
5097 #define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000
5098
REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0)5099 static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; }
5100
REG_A6XX_VFD_DEST_CNTL(uint32_t i0)5101 static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
5102
REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0)5103 static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
5104 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
5105 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)5106 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
5107 {
5108 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
5109 }
5110 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
5111 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)5112 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
5113 {
5114 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
5115 }
5116
5117 #define REG_A6XX_VFD_POWER_CNTL 0x0000a0f8
5118
5119 #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
5120
REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0)5121 static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; }
5122
5123 #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800
5124 #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000
5125 #define A6XX_SP_VS_CTRL_REG0_UNK21 0x00200000
5126 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
5127 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)5128 static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5129 {
5130 return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
5131 }
5132 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5133 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)5134 static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5135 {
5136 return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5137 }
5138 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5139 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)5140 static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5141 {
5142 return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5143 }
5144 #define A6XX_SP_VS_CTRL_REG0_UNK13 0x00002000
5145 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5146 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)5147 static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5148 {
5149 return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
5150 }
5151
5152 #define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801
5153
5154 #define REG_A6XX_SP_VS_PRIMITIVE_CNTL 0x0000a802
5155 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
5156 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT 0
A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val)5157 static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val)
5158 {
5159 return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK;
5160 }
5161 #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
5162 #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)5163 static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
5164 {
5165 return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
5166 }
5167
REG_A6XX_SP_VS_OUT(uint32_t i0)5168 static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
5169
REG_A6XX_SP_VS_OUT_REG(uint32_t i0)5170 static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
5171 #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
5172 #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)5173 static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
5174 {
5175 return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK;
5176 }
5177 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
5178 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)5179 static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
5180 {
5181 return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
5182 }
5183 #define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
5184 #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val)5185 static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
5186 {
5187 return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK;
5188 }
5189 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
5190 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)5191 static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
5192 {
5193 return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
5194 }
5195
REG_A6XX_SP_VS_VPC_DST(uint32_t i0)5196 static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
5197
REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0)5198 static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
5199 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
5200 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)5201 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
5202 {
5203 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
5204 }
5205 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
5206 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)5207 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
5208 {
5209 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
5210 }
5211 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
5212 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)5213 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
5214 {
5215 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
5216 }
5217 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
5218 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)5219 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
5220 {
5221 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
5222 }
5223
5224 #define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b
5225
5226 #define REG_A6XX_SP_VS_OBJ_START 0x0000a81c
5227 #define A6XX_SP_VS_OBJ_START__MASK 0xffffffff
5228 #define A6XX_SP_VS_OBJ_START__SHIFT 0
A6XX_SP_VS_OBJ_START(uint32_t val)5229 static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val)
5230 {
5231 return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK;
5232 }
5233
5234 #define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e
5235 #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5236 #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)5237 static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5238 {
5239 return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5240 }
5241 #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5242 #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)5243 static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5244 {
5245 return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5246 }
5247
5248 #define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f
5249 #define A6XX_SP_VS_PVT_MEM_ADDR__MASK 0xffffffff
5250 #define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT 0
A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val)5251 static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val)
5252 {
5253 return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK;
5254 }
5255
5256 #define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821
5257 #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5258 #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)5259 static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5260 {
5261 return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5262 }
5263 #define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5264
5265 #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822
5266
5267 #define REG_A6XX_SP_VS_CONFIG 0x0000a823
5268 #define A6XX_SP_VS_CONFIG_BINDLESS_TEX 0x00000001
5269 #define A6XX_SP_VS_CONFIG_BINDLESS_SAMP 0x00000002
5270 #define A6XX_SP_VS_CONFIG_BINDLESS_IBO 0x00000004
5271 #define A6XX_SP_VS_CONFIG_BINDLESS_UBO 0x00000008
5272 #define A6XX_SP_VS_CONFIG_ENABLED 0x00000100
5273 #define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00
5274 #define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9
A6XX_SP_VS_CONFIG_NTEX(uint32_t val)5275 static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val)
5276 {
5277 return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK;
5278 }
5279 #define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000
5280 #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)5281 static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
5282 {
5283 return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
5284 }
5285 #define A6XX_SP_VS_CONFIG_NIBO__MASK 0x1fc00000
5286 #define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22
A6XX_SP_VS_CONFIG_NIBO(uint32_t val)5287 static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
5288 {
5289 return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK;
5290 }
5291
5292 #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824
5293
5294 #define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825
5295 #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
5296 #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)5297 static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
5298 {
5299 return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
5300 }
5301
5302 #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830
5303 #define A6XX_SP_HS_CTRL_REG0_UNK20 0x00100000
5304 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001
5305 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0
A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)5306 static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5307 {
5308 return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK;
5309 }
5310 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5311 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)5312 static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5313 {
5314 return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5315 }
5316 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5317 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)5318 static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5319 {
5320 return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5321 }
5322 #define A6XX_SP_HS_CTRL_REG0_UNK13 0x00002000
5323 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5324 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)5325 static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5326 {
5327 return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
5328 }
5329
5330 #define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831
5331
5332 #define REG_A6XX_SP_HS_BRANCH_COND 0x0000a832
5333
5334 #define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833
5335
5336 #define REG_A6XX_SP_HS_OBJ_START 0x0000a834
5337 #define A6XX_SP_HS_OBJ_START__MASK 0xffffffff
5338 #define A6XX_SP_HS_OBJ_START__SHIFT 0
A6XX_SP_HS_OBJ_START(uint32_t val)5339 static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val)
5340 {
5341 return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK;
5342 }
5343
5344 #define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836
5345 #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5346 #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)5347 static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5348 {
5349 return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5350 }
5351 #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5352 #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)5353 static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5354 {
5355 return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5356 }
5357
5358 #define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837
5359 #define A6XX_SP_HS_PVT_MEM_ADDR__MASK 0xffffffff
5360 #define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT 0
A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val)5361 static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val)
5362 {
5363 return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK;
5364 }
5365
5366 #define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839
5367 #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5368 #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)5369 static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5370 {
5371 return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5372 }
5373 #define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5374
5375 #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a
5376
5377 #define REG_A6XX_SP_HS_CONFIG 0x0000a83b
5378 #define A6XX_SP_HS_CONFIG_BINDLESS_TEX 0x00000001
5379 #define A6XX_SP_HS_CONFIG_BINDLESS_SAMP 0x00000002
5380 #define A6XX_SP_HS_CONFIG_BINDLESS_IBO 0x00000004
5381 #define A6XX_SP_HS_CONFIG_BINDLESS_UBO 0x00000008
5382 #define A6XX_SP_HS_CONFIG_ENABLED 0x00000100
5383 #define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00
5384 #define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9
A6XX_SP_HS_CONFIG_NTEX(uint32_t val)5385 static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val)
5386 {
5387 return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK;
5388 }
5389 #define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000
5390 #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)5391 static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
5392 {
5393 return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
5394 }
5395 #define A6XX_SP_HS_CONFIG_NIBO__MASK 0x1fc00000
5396 #define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22
A6XX_SP_HS_CONFIG_NIBO(uint32_t val)5397 static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
5398 {
5399 return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK;
5400 }
5401
5402 #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c
5403
5404 #define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d
5405 #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
5406 #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)5407 static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
5408 {
5409 return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
5410 }
5411
5412 #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840
5413 #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x00100000
5414 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001
5415 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0
A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)5416 static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5417 {
5418 return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK;
5419 }
5420 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5421 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)5422 static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5423 {
5424 return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5425 }
5426 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5427 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)5428 static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5429 {
5430 return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5431 }
5432 #define A6XX_SP_DS_CTRL_REG0_UNK13 0x00002000
5433 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5434 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)5435 static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5436 {
5437 return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
5438 }
5439
5440 #define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841
5441
5442 #define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842
5443 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
5444 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT 0
A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val)5445 static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val)
5446 {
5447 return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK;
5448 }
5449 #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
5450 #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)5451 static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
5452 {
5453 return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
5454 }
5455
REG_A6XX_SP_DS_OUT(uint32_t i0)5456 static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
5457
REG_A6XX_SP_DS_OUT_REG(uint32_t i0)5458 static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
5459 #define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff
5460 #define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val)5461 static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
5462 {
5463 return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK;
5464 }
5465 #define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00
5466 #define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8
A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)5467 static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
5468 {
5469 return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
5470 }
5471 #define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000
5472 #define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val)5473 static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
5474 {
5475 return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK;
5476 }
5477 #define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000
5478 #define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24
A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)5479 static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
5480 {
5481 return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
5482 }
5483
REG_A6XX_SP_DS_VPC_DST(uint32_t i0)5484 static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
5485
REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0)5486 static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
5487 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
5488 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)5489 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
5490 {
5491 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
5492 }
5493 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
5494 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)5495 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
5496 {
5497 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
5498 }
5499 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
5500 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)5501 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
5502 {
5503 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
5504 }
5505 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
5506 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)5507 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
5508 {
5509 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
5510 }
5511
5512 #define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b
5513
5514 #define REG_A6XX_SP_DS_OBJ_START 0x0000a85c
5515 #define A6XX_SP_DS_OBJ_START__MASK 0xffffffff
5516 #define A6XX_SP_DS_OBJ_START__SHIFT 0
A6XX_SP_DS_OBJ_START(uint32_t val)5517 static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val)
5518 {
5519 return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK;
5520 }
5521
5522 #define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e
5523 #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5524 #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)5525 static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5526 {
5527 return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5528 }
5529 #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5530 #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)5531 static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5532 {
5533 return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5534 }
5535
5536 #define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f
5537 #define A6XX_SP_DS_PVT_MEM_ADDR__MASK 0xffffffff
5538 #define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT 0
A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val)5539 static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val)
5540 {
5541 return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK;
5542 }
5543
5544 #define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861
5545 #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5546 #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)5547 static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5548 {
5549 return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5550 }
5551 #define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5552
5553 #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862
5554
5555 #define REG_A6XX_SP_DS_CONFIG 0x0000a863
5556 #define A6XX_SP_DS_CONFIG_BINDLESS_TEX 0x00000001
5557 #define A6XX_SP_DS_CONFIG_BINDLESS_SAMP 0x00000002
5558 #define A6XX_SP_DS_CONFIG_BINDLESS_IBO 0x00000004
5559 #define A6XX_SP_DS_CONFIG_BINDLESS_UBO 0x00000008
5560 #define A6XX_SP_DS_CONFIG_ENABLED 0x00000100
5561 #define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00
5562 #define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9
A6XX_SP_DS_CONFIG_NTEX(uint32_t val)5563 static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val)
5564 {
5565 return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK;
5566 }
5567 #define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000
5568 #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)5569 static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
5570 {
5571 return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
5572 }
5573 #define A6XX_SP_DS_CONFIG_NIBO__MASK 0x1fc00000
5574 #define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22
A6XX_SP_DS_CONFIG_NIBO(uint32_t val)5575 static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
5576 {
5577 return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK;
5578 }
5579
5580 #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864
5581
5582 #define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865
5583 #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
5584 #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)5585 static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
5586 {
5587 return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
5588 }
5589
5590 #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870
5591 #define A6XX_SP_GS_CTRL_REG0_UNK20 0x00100000
5592 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001
5593 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0
A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)5594 static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5595 {
5596 return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK;
5597 }
5598 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5599 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)5600 static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5601 {
5602 return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5603 }
5604 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5605 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)5606 static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5607 {
5608 return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5609 }
5610 #define A6XX_SP_GS_CTRL_REG0_UNK13 0x00002000
5611 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5612 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)5613 static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5614 {
5615 return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
5616 }
5617
5618 #define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871
5619
5620 #define REG_A6XX_SP_GS_BRANCH_COND 0x0000a872
5621
5622 #define REG_A6XX_SP_GS_PRIMITIVE_CNTL 0x0000a873
5623 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
5624 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT 0
A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val)5625 static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val)
5626 {
5627 return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK;
5628 }
5629 #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
5630 #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)5631 static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
5632 {
5633 return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
5634 }
5635
REG_A6XX_SP_GS_OUT(uint32_t i0)5636 static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
5637
REG_A6XX_SP_GS_OUT_REG(uint32_t i0)5638 static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
5639 #define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff
5640 #define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val)5641 static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
5642 {
5643 return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK;
5644 }
5645 #define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00000f00
5646 #define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 8
A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)5647 static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
5648 {
5649 return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
5650 }
5651 #define A6XX_SP_GS_OUT_REG_B_REGID__MASK 0x00ff0000
5652 #define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val)5653 static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
5654 {
5655 return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK;
5656 }
5657 #define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x0f000000
5658 #define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 24
A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)5659 static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
5660 {
5661 return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
5662 }
5663
REG_A6XX_SP_GS_VPC_DST(uint32_t i0)5664 static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
5665
REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0)5666 static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
5667 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
5668 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)5669 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
5670 {
5671 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
5672 }
5673 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
5674 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)5675 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
5676 {
5677 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
5678 }
5679 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
5680 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)5681 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
5682 {
5683 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
5684 }
5685 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
5686 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)5687 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
5688 {
5689 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
5690 }
5691
5692 #define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c
5693
5694 #define REG_A6XX_SP_GS_OBJ_START 0x0000a88d
5695 #define A6XX_SP_GS_OBJ_START__MASK 0xffffffff
5696 #define A6XX_SP_GS_OBJ_START__SHIFT 0
A6XX_SP_GS_OBJ_START(uint32_t val)5697 static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val)
5698 {
5699 return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK;
5700 }
5701
5702 #define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f
5703 #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5704 #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)5705 static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5706 {
5707 return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5708 }
5709 #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5710 #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)5711 static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5712 {
5713 return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5714 }
5715
5716 #define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890
5717 #define A6XX_SP_GS_PVT_MEM_ADDR__MASK 0xffffffff
5718 #define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT 0
A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val)5719 static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val)
5720 {
5721 return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK;
5722 }
5723
5724 #define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892
5725 #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5726 #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)5727 static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5728 {
5729 return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5730 }
5731 #define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5732
5733 #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893
5734
5735 #define REG_A6XX_SP_GS_CONFIG 0x0000a894
5736 #define A6XX_SP_GS_CONFIG_BINDLESS_TEX 0x00000001
5737 #define A6XX_SP_GS_CONFIG_BINDLESS_SAMP 0x00000002
5738 #define A6XX_SP_GS_CONFIG_BINDLESS_IBO 0x00000004
5739 #define A6XX_SP_GS_CONFIG_BINDLESS_UBO 0x00000008
5740 #define A6XX_SP_GS_CONFIG_ENABLED 0x00000100
5741 #define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00
5742 #define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9
A6XX_SP_GS_CONFIG_NTEX(uint32_t val)5743 static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val)
5744 {
5745 return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK;
5746 }
5747 #define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000
5748 #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)5749 static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
5750 {
5751 return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
5752 }
5753 #define A6XX_SP_GS_CONFIG_NIBO__MASK 0x1fc00000
5754 #define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22
A6XX_SP_GS_CONFIG_NIBO(uint32_t val)5755 static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
5756 {
5757 return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK;
5758 }
5759
5760 #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895
5761
5762 #define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896
5763 #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
5764 #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)5765 static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
5766 {
5767 return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
5768 }
5769
5770 #define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0
5771 #define A6XX_SP_VS_TEX_SAMP__MASK 0xffffffff
5772 #define A6XX_SP_VS_TEX_SAMP__SHIFT 0
A6XX_SP_VS_TEX_SAMP(uint32_t val)5773 static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val)
5774 {
5775 return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK;
5776 }
5777
5778 #define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2
5779 #define A6XX_SP_HS_TEX_SAMP__MASK 0xffffffff
5780 #define A6XX_SP_HS_TEX_SAMP__SHIFT 0
A6XX_SP_HS_TEX_SAMP(uint32_t val)5781 static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val)
5782 {
5783 return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK;
5784 }
5785
5786 #define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4
5787 #define A6XX_SP_DS_TEX_SAMP__MASK 0xffffffff
5788 #define A6XX_SP_DS_TEX_SAMP__SHIFT 0
A6XX_SP_DS_TEX_SAMP(uint32_t val)5789 static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val)
5790 {
5791 return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK;
5792 }
5793
5794 #define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6
5795 #define A6XX_SP_GS_TEX_SAMP__MASK 0xffffffff
5796 #define A6XX_SP_GS_TEX_SAMP__SHIFT 0
A6XX_SP_GS_TEX_SAMP(uint32_t val)5797 static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val)
5798 {
5799 return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK;
5800 }
5801
5802 #define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8
5803 #define A6XX_SP_VS_TEX_CONST__MASK 0xffffffff
5804 #define A6XX_SP_VS_TEX_CONST__SHIFT 0
A6XX_SP_VS_TEX_CONST(uint32_t val)5805 static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val)
5806 {
5807 return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK;
5808 }
5809
5810 #define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa
5811 #define A6XX_SP_HS_TEX_CONST__MASK 0xffffffff
5812 #define A6XX_SP_HS_TEX_CONST__SHIFT 0
A6XX_SP_HS_TEX_CONST(uint32_t val)5813 static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val)
5814 {
5815 return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK;
5816 }
5817
5818 #define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac
5819 #define A6XX_SP_DS_TEX_CONST__MASK 0xffffffff
5820 #define A6XX_SP_DS_TEX_CONST__SHIFT 0
A6XX_SP_DS_TEX_CONST(uint32_t val)5821 static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val)
5822 {
5823 return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK;
5824 }
5825
5826 #define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae
5827 #define A6XX_SP_GS_TEX_CONST__MASK 0xffffffff
5828 #define A6XX_SP_GS_TEX_CONST__SHIFT 0
A6XX_SP_GS_TEX_CONST(uint32_t val)5829 static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val)
5830 {
5831 return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK;
5832 }
5833
5834 #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980
5835 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5836 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)5837 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
5838 {
5839 return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
5840 }
5841 #define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000
5842 #define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
5843 #define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000
5844 #define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000
5845 #define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000
5846 #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
5847 #define A6XX_SP_FS_CTRL_REG0_UNK27__MASK 0x18000000
5848 #define A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT 27
A6XX_SP_FS_CTRL_REG0_UNK27(uint32_t val)5849 static inline uint32_t A6XX_SP_FS_CTRL_REG0_UNK27(uint32_t val)
5850 {
5851 return ((val) << A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT) & A6XX_SP_FS_CTRL_REG0_UNK27__MASK;
5852 }
5853 #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
5854 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
5855 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)5856 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5857 {
5858 return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
5859 }
5860 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5861 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)5862 static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5863 {
5864 return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5865 }
5866 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5867 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)5868 static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5869 {
5870 return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5871 }
5872 #define A6XX_SP_FS_CTRL_REG0_UNK13 0x00002000
5873 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5874 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)5875 static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5876 {
5877 return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
5878 }
5879
5880 #define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981
5881
5882 #define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982
5883
5884 #define REG_A6XX_SP_FS_OBJ_START 0x0000a983
5885 #define A6XX_SP_FS_OBJ_START__MASK 0xffffffff
5886 #define A6XX_SP_FS_OBJ_START__SHIFT 0
A6XX_SP_FS_OBJ_START(uint32_t val)5887 static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val)
5888 {
5889 return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK;
5890 }
5891
5892 #define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985
5893 #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5894 #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)5895 static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5896 {
5897 return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5898 }
5899 #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5900 #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)5901 static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5902 {
5903 return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5904 }
5905
5906 #define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986
5907 #define A6XX_SP_FS_PVT_MEM_ADDR__MASK 0xffffffff
5908 #define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT 0
A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val)5909 static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val)
5910 {
5911 return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK;
5912 }
5913
5914 #define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988
5915 #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5916 #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)5917 static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5918 {
5919 return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5920 }
5921 #define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5922
5923 #define REG_A6XX_SP_BLEND_CNTL 0x0000a989
5924 #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
5925 #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)5926 static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
5927 {
5928 return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
5929 }
5930 #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100
5931 #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200
5932 #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
5933
5934 #define REG_A6XX_SP_SRGB_CNTL 0x0000a98a
5935 #define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001
5936 #define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002
5937 #define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004
5938 #define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008
5939 #define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010
5940 #define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020
5941 #define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040
5942 #define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080
5943
5944 #define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b
5945 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f
5946 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0
A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val)5947 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val)
5948 {
5949 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK;
5950 }
5951 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0
5952 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4
A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val)5953 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val)
5954 {
5955 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK;
5956 }
5957 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00
5958 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8
A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val)5959 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val)
5960 {
5961 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK;
5962 }
5963 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000
5964 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12
A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val)5965 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val)
5966 {
5967 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK;
5968 }
5969 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000
5970 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16
A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val)5971 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val)
5972 {
5973 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK;
5974 }
5975 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000
5976 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20
A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val)5977 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val)
5978 {
5979 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK;
5980 }
5981 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000
5982 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24
A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val)5983 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val)
5984 {
5985 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK;
5986 }
5987 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000
5988 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28
A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val)5989 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val)
5990 {
5991 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK;
5992 }
5993
5994 #define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c
5995 #define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001
5996 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00
5997 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8
A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)5998 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)
5999 {
6000 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK;
6001 }
6002 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000
6003 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16
A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val)6004 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val)
6005 {
6006 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK;
6007 }
6008 #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK 0xff000000
6009 #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT 24
A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val)6010 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val)
6011 {
6012 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK;
6013 }
6014
6015 #define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d
6016 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
6017 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0
A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)6018 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)
6019 {
6020 return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
6021 }
6022
REG_A6XX_SP_FS_OUTPUT(uint32_t i0)6023 static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
6024
REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0)6025 static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
6026 #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
6027 #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)6028 static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
6029 {
6030 return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
6031 }
6032 #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
6033
REG_A6XX_SP_FS_MRT(uint32_t i0)6034 static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
6035
REG_A6XX_SP_FS_MRT_REG(uint32_t i0)6036 static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
6037 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
6038 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val)6039 static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val)
6040 {
6041 return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
6042 }
6043 #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
6044 #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
6045 #define A6XX_SP_FS_MRT_REG_UNK10 0x00000400
6046
6047 #define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e
6048 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007
6049 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT 0
A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val)6050 static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val)
6051 {
6052 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK;
6053 }
6054 #define A6XX_SP_FS_PREFETCH_CNTL_UNK3 0x00000008
6055 #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK 0x00000ff0
6056 #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT 4
A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val)6057 static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val)
6058 {
6059 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK;
6060 }
6061 #define A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK 0x00007000
6062 #define A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT 12
A6XX_SP_FS_PREFETCH_CNTL_UNK12(uint32_t val)6063 static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK12(uint32_t val)
6064 {
6065 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK;
6066 }
6067
REG_A6XX_SP_FS_PREFETCH(uint32_t i0)6068 static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
6069
REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0)6070 static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
6071 #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f
6072 #define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0
A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val)6073 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val)
6074 {
6075 return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK;
6076 }
6077 #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000780
6078 #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7
A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val)6079 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val)
6080 {
6081 return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK;
6082 }
6083 #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x0000f800
6084 #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 11
A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val)6085 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val)
6086 {
6087 return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK;
6088 }
6089 #define A6XX_SP_FS_PREFETCH_CMD_DST__MASK 0x003f0000
6090 #define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT 16
A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val)6091 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val)
6092 {
6093 return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK;
6094 }
6095 #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x03c00000
6096 #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 22
A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val)6097 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val)
6098 {
6099 return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK;
6100 }
6101 #define A6XX_SP_FS_PREFETCH_CMD_HALF 0x04000000
6102 #define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK 0xf8000000
6103 #define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 27
A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val)6104 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val)
6105 {
6106 return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK;
6107 }
6108
REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0)6109 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
6110
REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0)6111 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
6112 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff
6113 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0
A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)6114 static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)
6115 {
6116 return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK;
6117 }
6118 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0xffff0000
6119 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16
A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)6120 static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)
6121 {
6122 return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK;
6123 }
6124
6125 #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7
6126
6127 #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8
6128
6129 #define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9
6130 #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
6131 #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)6132 static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
6133 {
6134 return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
6135 }
6136
6137 #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0
6138 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
6139 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)6140 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
6141 {
6142 return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
6143 }
6144 #define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000
6145 #define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000
6146 #define A6XX_SP_CS_CTRL_REG0_SEPARATEPROLOG 0x00800000
6147 #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
6148 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001
6149 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0
A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)6150 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
6151 {
6152 return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK;
6153 }
6154 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
6155 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)6156 static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
6157 {
6158 return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
6159 }
6160 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
6161 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)6162 static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
6163 {
6164 return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
6165 }
6166 #define A6XX_SP_CS_CTRL_REG0_UNK13 0x00002000
6167 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
6168 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)6169 static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
6170 {
6171 return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
6172 }
6173
6174 #define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1
6175 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f
6176 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT 0
A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val)6177 static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val)
6178 {
6179 return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK;
6180 }
6181 #define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 0x00000020
6182 #define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 0x00000040
6183
6184 #define REG_A6XX_SP_CS_BRANCH_COND 0x0000a9b2
6185
6186 #define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3
6187
6188 #define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4
6189 #define A6XX_SP_CS_OBJ_START__MASK 0xffffffff
6190 #define A6XX_SP_CS_OBJ_START__SHIFT 0
A6XX_SP_CS_OBJ_START(uint32_t val)6191 static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val)
6192 {
6193 return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK;
6194 }
6195
6196 #define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6
6197 #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
6198 #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)6199 static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
6200 {
6201 return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
6202 }
6203 #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
6204 #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)6205 static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
6206 {
6207 return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
6208 }
6209
6210 #define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7
6211 #define A6XX_SP_CS_PVT_MEM_ADDR__MASK 0xffffffff
6212 #define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT 0
A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val)6213 static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val)
6214 {
6215 return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK;
6216 }
6217
6218 #define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9
6219 #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
6220 #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)6221 static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
6222 {
6223 return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
6224 }
6225 #define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
6226
6227 #define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba
6228
6229 #define REG_A6XX_SP_CS_CONFIG 0x0000a9bb
6230 #define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001
6231 #define A6XX_SP_CS_CONFIG_BINDLESS_SAMP 0x00000002
6232 #define A6XX_SP_CS_CONFIG_BINDLESS_IBO 0x00000004
6233 #define A6XX_SP_CS_CONFIG_BINDLESS_UBO 0x00000008
6234 #define A6XX_SP_CS_CONFIG_ENABLED 0x00000100
6235 #define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00
6236 #define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9
A6XX_SP_CS_CONFIG_NTEX(uint32_t val)6237 static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val)
6238 {
6239 return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK;
6240 }
6241 #define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000
6242 #define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_CS_CONFIG_NSAMP(uint32_t val)6243 static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val)
6244 {
6245 return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK;
6246 }
6247 #define A6XX_SP_CS_CONFIG_NIBO__MASK 0x1fc00000
6248 #define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22
A6XX_SP_CS_CONFIG_NIBO(uint32_t val)6249 static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
6250 {
6251 return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK;
6252 }
6253
6254 #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc
6255
6256 #define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd
6257 #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
6258 #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)6259 static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
6260 {
6261 return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
6262 }
6263
6264 #define REG_A6XX_SP_CS_CNTL_0 0x0000a9c2
6265 #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
6266 #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT 0
A6XX_SP_CS_CNTL_0_WGIDCONSTID(uint32_t val)6267 static inline uint32_t A6XX_SP_CS_CNTL_0_WGIDCONSTID(uint32_t val)
6268 {
6269 return ((val) << A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK;
6270 }
6271 #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00
6272 #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT 8
A6XX_SP_CS_CNTL_0_WGSIZECONSTID(uint32_t val)6273 static inline uint32_t A6XX_SP_CS_CNTL_0_WGSIZECONSTID(uint32_t val)
6274 {
6275 return ((val) << A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK;
6276 }
6277 #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000
6278 #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16
A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)6279 static inline uint32_t A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)
6280 {
6281 return ((val) << A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK;
6282 }
6283 #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
6284 #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT 24
A6XX_SP_CS_CNTL_0_LOCALIDREGID(uint32_t val)6285 static inline uint32_t A6XX_SP_CS_CNTL_0_LOCALIDREGID(uint32_t val)
6286 {
6287 return ((val) << A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK;
6288 }
6289
6290 #define REG_A6XX_SP_CS_CNTL_1 0x0000a9c3
6291 #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff
6292 #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0
A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)6293 static inline uint32_t A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
6294 {
6295 return ((val) << A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
6296 }
6297 #define A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE 0x00000100
6298 #define A6XX_SP_CS_CNTL_1_THREADSIZE__MASK 0x00000200
6299 #define A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT 9
A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)6300 static inline uint32_t A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
6301 {
6302 return ((val) << A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_SP_CS_CNTL_1_THREADSIZE__MASK;
6303 }
6304 #define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400
6305
6306 #define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0
6307 #define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff
6308 #define A6XX_SP_FS_TEX_SAMP__SHIFT 0
A6XX_SP_FS_TEX_SAMP(uint32_t val)6309 static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val)
6310 {
6311 return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK;
6312 }
6313
6314 #define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2
6315 #define A6XX_SP_CS_TEX_SAMP__MASK 0xffffffff
6316 #define A6XX_SP_CS_TEX_SAMP__SHIFT 0
A6XX_SP_CS_TEX_SAMP(uint32_t val)6317 static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val)
6318 {
6319 return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK;
6320 }
6321
6322 #define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4
6323 #define A6XX_SP_FS_TEX_CONST__MASK 0xffffffff
6324 #define A6XX_SP_FS_TEX_CONST__SHIFT 0
A6XX_SP_FS_TEX_CONST(uint32_t val)6325 static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val)
6326 {
6327 return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK;
6328 }
6329
6330 #define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6
6331 #define A6XX_SP_CS_TEX_CONST__MASK 0xffffffff
6332 #define A6XX_SP_CS_TEX_CONST__SHIFT 0
A6XX_SP_CS_TEX_CONST(uint32_t val)6333 static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val)
6334 {
6335 return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK;
6336 }
6337
REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0)6338 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6339
REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0)6340 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6341
6342 #define REG_A6XX_SP_CS_IBO 0x0000a9f2
6343 #define A6XX_SP_CS_IBO__MASK 0xffffffff
6344 #define A6XX_SP_CS_IBO__SHIFT 0
A6XX_SP_CS_IBO(uint32_t val)6345 static inline uint32_t A6XX_SP_CS_IBO(uint32_t val)
6346 {
6347 return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK;
6348 }
6349
6350 #define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00
6351
6352 #define REG_A6XX_SP_MODE_CONTROL 0x0000ab00
6353 #define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001
6354 #define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK 0x00000006
6355 #define A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT 1
A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val)6356 static inline uint32_t A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val)
6357 {
6358 return ((val) << A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT) & A6XX_SP_MODE_CONTROL_ISAMMODE__MASK;
6359 }
6360 #define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008
6361
6362 #define REG_A6XX_SP_FS_CONFIG 0x0000ab04
6363 #define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001
6364 #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002
6365 #define A6XX_SP_FS_CONFIG_BINDLESS_IBO 0x00000004
6366 #define A6XX_SP_FS_CONFIG_BINDLESS_UBO 0x00000008
6367 #define A6XX_SP_FS_CONFIG_ENABLED 0x00000100
6368 #define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00
6369 #define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9
A6XX_SP_FS_CONFIG_NTEX(uint32_t val)6370 static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val)
6371 {
6372 return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK;
6373 }
6374 #define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000
6375 #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)6376 static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
6377 {
6378 return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
6379 }
6380 #define A6XX_SP_FS_CONFIG_NIBO__MASK 0x1fc00000
6381 #define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22
A6XX_SP_FS_CONFIG_NIBO(uint32_t val)6382 static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)
6383 {
6384 return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK;
6385 }
6386
6387 #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05
6388
REG_A6XX_SP_BINDLESS_BASE(uint32_t i0)6389 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6390
REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0)6391 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6392
6393 #define REG_A6XX_SP_IBO 0x0000ab1a
6394 #define A6XX_SP_IBO__MASK 0xffffffff
6395 #define A6XX_SP_IBO__SHIFT 0
A6XX_SP_IBO(uint32_t val)6396 static inline uint32_t A6XX_SP_IBO(uint32_t val)
6397 {
6398 return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK;
6399 }
6400
6401 #define REG_A6XX_SP_IBO_COUNT 0x0000ab20
6402
6403 #define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0
6404 #define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001
6405 #define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002
6406 #define A6XX_SP_2D_DST_FORMAT_UINT 0x00000004
6407 #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8
6408 #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3
A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val)6409 static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val)
6410 {
6411 return ((val) << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK;
6412 }
6413 #define A6XX_SP_2D_DST_FORMAT_SRGB 0x00000800
6414 #define A6XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000
6415 #define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT 12
A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val)6416 static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val)
6417 {
6418 return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK;
6419 }
6420
6421 #define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00
6422
6423 #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
6424
6425 #define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
6426
6427 #define REG_A6XX_SP_CHICKEN_BITS 0x0000ae03
6428
6429 #define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04
6430 #define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008
6431
6432 #define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f
6433 #define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001
6434 #define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002
6435 #define A6XX_SP_PERFCTR_ENABLE_DS 0x00000004
6436 #define A6XX_SP_PERFCTR_ENABLE_GS 0x00000008
6437 #define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010
6438 #define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020
6439
REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0)6440 static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; }
6441
6442 #define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22
6443
6444 #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180
6445 #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff
6446 #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0
A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)6447 static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
6448 {
6449 return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK;
6450 }
6451
6452 #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182
6453
6454 #define REG_A6XX_SP_UNKNOWN_B183 0x0000b183
6455
6456 #define REG_A6XX_SP_UNKNOWN_B190 0x0000b190
6457
6458 #define REG_A6XX_SP_UNKNOWN_B191 0x0000b191
6459
6460 #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300
6461 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
6462 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)6463 static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
6464 {
6465 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
6466 }
6467 #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK 0x0000000c
6468 #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT 2
A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val)6469 static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val)
6470 {
6471 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK;
6472 }
6473
6474 #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301
6475 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
6476 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)6477 static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
6478 {
6479 return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
6480 }
6481 #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
6482
6483 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302
6484 #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff
6485 #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0
A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)6486 static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
6487 {
6488 return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK;
6489 }
6490
6491 #define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304
6492 #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001
6493 #define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
6494
6495 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 0x0000b305
6496 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
6497 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)6498 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
6499 {
6500 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
6501 }
6502 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
6503 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)6504 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
6505 {
6506 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
6507 }
6508 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
6509 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)6510 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
6511 {
6512 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
6513 }
6514 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
6515 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)6516 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
6517 {
6518 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
6519 }
6520 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
6521 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)6522 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
6523 {
6524 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
6525 }
6526 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
6527 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)6528 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
6529 {
6530 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
6531 }
6532 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
6533 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)6534 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
6535 {
6536 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
6537 }
6538 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
6539 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)6540 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
6541 {
6542 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
6543 }
6544
6545 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306
6546 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
6547 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)6548 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
6549 {
6550 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
6551 }
6552 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
6553 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)6554 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
6555 {
6556 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
6557 }
6558 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
6559 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)6560 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
6561 {
6562 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
6563 }
6564 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
6565 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)6566 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
6567 {
6568 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
6569 }
6570 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
6571 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)6572 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
6573 {
6574 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
6575 }
6576 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
6577 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)6578 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
6579 {
6580 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
6581 }
6582 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
6583 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)6584 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
6585 {
6586 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
6587 }
6588 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
6589 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)6590 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
6591 {
6592 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
6593 }
6594
6595 #define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307
6596 #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00003fff
6597 #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0
A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)6598 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
6599 {
6600 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
6601 }
6602 #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x3fff0000
6603 #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16
A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)6604 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
6605 {
6606 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
6607 }
6608
6609 #define REG_A6XX_SP_TP_MODE_CNTL 0x0000b309
6610 #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK 0x00000003
6611 #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT 0
A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val)6612 static inline uint32_t A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val)
6613 {
6614 return ((val) << A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT) & A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK;
6615 }
6616 #define A6XX_SP_TP_MODE_CNTL_UNK3__MASK 0x000000fc
6617 #define A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT 2
A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val)6618 static inline uint32_t A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val)
6619 {
6620 return ((val) << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK;
6621 }
6622
6623 #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0
6624 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
6625 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val)6626 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val)
6627 {
6628 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;
6629 }
6630 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
6631 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8
A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)6632 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)
6633 {
6634 return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK;
6635 }
6636 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
6637 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)6638 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
6639 {
6640 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK;
6641 }
6642 #define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000
6643 #define A6XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000
6644 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000
6645 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14
A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)6646 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)
6647 {
6648 return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;
6649 }
6650 #define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000
6651 #define A6XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000
6652 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000
6653 #define A6XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000
6654 #define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000
6655 #define A6XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000
6656 #define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000
6657 #define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000
6658 #define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23
A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val)6659 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val)
6660 {
6661 return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK;
6662 }
6663 #define A6XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000
6664
6665 #define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1
6666 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff
6667 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0
A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)6668 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)
6669 {
6670 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK;
6671 }
6672 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000
6673 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15
A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)6674 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
6675 {
6676 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
6677 }
6678
6679 #define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2
6680 #define A6XX_SP_PS_2D_SRC__MASK 0xffffffff
6681 #define A6XX_SP_PS_2D_SRC__SHIFT 0
A6XX_SP_PS_2D_SRC(uint32_t val)6682 static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val)
6683 {
6684 return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK;
6685 }
6686
6687 #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4
6688 #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff
6689 #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0
A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val)6690 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val)
6691 {
6692 return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK;
6693 }
6694 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00
6695 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)6696 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
6697 {
6698 return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
6699 }
6700
6701 #define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5
6702 #define A6XX_SP_PS_2D_SRC_PLANE1__MASK 0xffffffff
6703 #define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT 0
A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val)6704 static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val)
6705 {
6706 return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK;
6707 }
6708
6709 #define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7
6710 #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff
6711 #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0
A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val)6712 static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val)
6713 {
6714 return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK;
6715 }
6716
6717 #define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8
6718 #define A6XX_SP_PS_2D_SRC_PLANE2__MASK 0xffffffff
6719 #define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT 0
A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val)6720 static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val)
6721 {
6722 return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK;
6723 }
6724
6725 #define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca
6726 #define A6XX_SP_PS_2D_SRC_FLAGS__MASK 0xffffffff
6727 #define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT 0
A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val)6728 static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val)
6729 {
6730 return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK;
6731 }
6732
6733 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc
6734 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff
6735 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0
A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val)6736 static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val)
6737 {
6738 return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK;
6739 }
6740
6741 #define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd
6742
6743 #define REG_A6XX_SP_PS_UNKNOWN_B4CE 0x0000b4ce
6744
6745 #define REG_A6XX_SP_PS_UNKNOWN_B4CF 0x0000b4cf
6746
6747 #define REG_A6XX_SP_PS_UNKNOWN_B4D0 0x0000b4d0
6748
6749 #define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1
6750 #define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff
6751 #define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0
A6XX_SP_WINDOW_OFFSET_X(uint32_t val)6752 static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
6753 {
6754 return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
6755 }
6756 #define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000
6757 #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16
A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)6758 static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
6759 {
6760 return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
6761 }
6762
6763 #define REG_A6XX_TPL1_DBG_ECO_CNTL 0x0000b600
6764
6765 #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601
6766
6767 #define REG_A6XX_TPL1_UNKNOWN_B602 0x0000b602
6768
6769 #define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604
6770 #define A6XX_TPL1_NC_MODE_CNTL_MODE 0x00000001
6771 #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006
6772 #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT 1
A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val)6773 static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
6774 {
6775 return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK;
6776 }
6777 #define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008
6778 #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000010
6779 #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT 4
A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val)6780 static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
6781 {
6782 return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK;
6783 }
6784 #define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK 0x000000c0
6785 #define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT 6
A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val)6786 static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val)
6787 {
6788 return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK;
6789 }
6790
6791 #define REG_A6XX_TPL1_UNKNOWN_B605 0x0000b605
6792
6793 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608
6794
6795 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609
6796
6797 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a
6798
6799 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b
6800
6801 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c
6802
REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0)6803 static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; }
6804
6805 #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800
6806 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff
6807 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)6808 static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
6809 {
6810 return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
6811 }
6812 #define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100
6813
6814 #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801
6815 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff
6816 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)6817 static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
6818 {
6819 return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
6820 }
6821 #define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100
6822
6823 #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802
6824 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff
6825 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)6826 static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
6827 {
6828 return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
6829 }
6830 #define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100
6831
6832 #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803
6833 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff
6834 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)6835 static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
6836 {
6837 return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
6838 }
6839 #define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100
6840
6841 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820
6842
6843 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821
6844 #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK 0xffffffff
6845 #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT 0
A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val)6846 static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val)
6847 {
6848 return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK;
6849 }
6850
6851 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823
6852
6853 #define REG_A6XX_HLSQ_FS_CNTL_0 0x0000b980
6854 #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001
6855 #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0
A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val)6856 static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val)
6857 {
6858 return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK;
6859 }
6860 #define A6XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002
6861 #define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc
6862 #define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2
A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val)6863 static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val)
6864 {
6865 return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK;
6866 }
6867
6868 #define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981
6869
6870 #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982
6871
6872 #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983
6873 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
6874 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)6875 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
6876 {
6877 return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
6878 }
6879 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00
6880 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8
A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)6881 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
6882 {
6883 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
6884 }
6885 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000
6886 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16
A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)6887 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
6888 {
6889 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
6890 }
6891 #define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000
6892 #define A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24
A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)6893 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)
6894 {
6895 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK;
6896 }
6897
6898 #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984
6899 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
6900 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)6901 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
6902 {
6903 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
6904 }
6905 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
6906 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)6907 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
6908 {
6909 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
6910 }
6911 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
6912 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)6913 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
6914 {
6915 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
6916 }
6917 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
6918 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)6919 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
6920 {
6921 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
6922 }
6923
6924 #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985
6925 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
6926 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)6927 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
6928 {
6929 return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
6930 }
6931 #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
6932 #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)6933 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
6934 {
6935 return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
6936 }
6937 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
6938 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)6939 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
6940 {
6941 return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
6942 }
6943 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
6944 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)6945 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
6946 {
6947 return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
6948 }
6949
6950 #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986
6951 #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff
6952 #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0
A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val)6953 static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val)
6954 {
6955 return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK;
6956 }
6957 #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00
6958 #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8
A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val)6959 static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val)
6960 {
6961 return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK;
6962 }
6963
6964 #define REG_A6XX_HLSQ_CS_CNTL 0x0000b987
6965 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff
6966 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)6967 static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
6968 {
6969 return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK;
6970 }
6971 #define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100
6972
6973 #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990
6974 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
6975 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)6976 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
6977 {
6978 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
6979 }
6980 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
6981 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)6982 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
6983 {
6984 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
6985 }
6986 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
6987 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)6988 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
6989 {
6990 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
6991 }
6992 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
6993 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)6994 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
6995 {
6996 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
6997 }
6998
6999 #define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991
7000 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff
7001 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)7002 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
7003 {
7004 return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
7005 }
7006
7007 #define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992
7008 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff
7009 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)7010 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
7011 {
7012 return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
7013 }
7014
7015 #define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993
7016 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff
7017 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)7018 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
7019 {
7020 return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
7021 }
7022
7023 #define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994
7024 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff
7025 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)7026 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
7027 {
7028 return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
7029 }
7030
7031 #define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995
7032 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff
7033 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)7034 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
7035 {
7036 return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
7037 }
7038
7039 #define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996
7040 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff
7041 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)7042 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
7043 {
7044 return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
7045 }
7046
7047 #define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997
7048 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
7049 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)7050 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
7051 {
7052 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
7053 }
7054 #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00
7055 #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT 8
A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val)7056 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val)
7057 {
7058 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK;
7059 }
7060 #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000
7061 #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16
A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)7062 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)
7063 {
7064 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK;
7065 }
7066 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
7067 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)7068 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
7069 {
7070 return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
7071 }
7072
7073 #define REG_A6XX_HLSQ_CS_CNTL_1 0x0000b998
7074 #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff
7075 #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0
A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)7076 static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
7077 {
7078 return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
7079 }
7080 #define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE 0x00000100
7081 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200
7082 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9
A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)7083 static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
7084 {
7085 return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK;
7086 }
7087 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400
7088
7089 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999
7090
7091 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a
7092
7093 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b
7094
7095 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0
7096
7097 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1
7098 #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK 0xffffffff
7099 #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT 0
A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val)7100 static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val)
7101 {
7102 return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK;
7103 }
7104
7105 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3
7106
REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0)7107 static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
7108
REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0)7109 static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
7110
7111 #define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 0x0000b9d0
7112 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK 0x0000001f
7113 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT 0
A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(uint32_t val)7114 static inline uint32_t A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(uint32_t val)
7115 {
7116 return ((val) << A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT) & A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK;
7117 }
7118 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5 0x00000020
7119 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6 0x00000040
7120
7121 #define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00
7122 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK 0x000000ff
7123 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT 0
A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val)7124 static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val)
7125 {
7126 return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK;
7127 }
7128
7129 #define REG_A6XX_HLSQ_DISPATCH_CMD 0x0000bb01
7130 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK 0x000000ff
7131 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT 0
A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val)7132 static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val)
7133 {
7134 return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK;
7135 }
7136
7137 #define REG_A6XX_HLSQ_EVENT_CMD 0x0000bb02
7138 #define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK 0x00ff0000
7139 #define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT 16
A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val)7140 static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val)
7141 {
7142 return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK;
7143 }
7144 #define A6XX_HLSQ_EVENT_CMD_EVENT__MASK 0x0000007f
7145 #define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT 0
A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val)7146 static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val)
7147 {
7148 return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK;
7149 }
7150
7151 #define REG_A6XX_HLSQ_INVALIDATE_CMD 0x0000bb08
7152 #define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001
7153 #define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002
7154 #define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004
7155 #define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008
7156 #define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010
7157 #define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020
7158 #define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040
7159 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080
7160 #define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST 0x00080000
7161 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST 0x00000100
7162 #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x00003e00
7163 #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9
A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val)7164 static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val)
7165 {
7166 return ((val) << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK;
7167 }
7168 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x0007c000
7169 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 14
A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val)7170 static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val)
7171 {
7172 return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK;
7173 }
7174
7175 #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10
7176 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff
7177 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)7178 static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
7179 {
7180 return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
7181 }
7182 #define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100
7183
7184 #define REG_A6XX_HLSQ_SHARED_CONSTS 0x0000bb11
7185 #define A6XX_HLSQ_SHARED_CONSTS_ENABLE 0x00000001
7186
REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0)7187 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
7188
REG_A6XX_HLSQ_BINDLESS_BASE_ADDR(uint32_t i0)7189 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
7190
7191 #define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80
7192 #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00
7193 #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT 8
A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val)7194 static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val)
7195 {
7196 return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK;
7197 }
7198 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK 0x0000007f
7199 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT 0
A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val)7200 static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
7201 {
7202 return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK;
7203 }
7204
7205 #define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00
7206
7207 #define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01
7208
7209 #define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04
7210
7211 #define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05
7212
7213 #define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08
7214
REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0)7215 static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; }
7216
7217 #define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22
7218
7219 #define REG_A6XX_CP_EVENT_START 0x0000d600
7220 #define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff
7221 #define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0
A6XX_CP_EVENT_START_STATE_ID(uint32_t val)7222 static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val)
7223 {
7224 return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK;
7225 }
7226
7227 #define REG_A6XX_CP_EVENT_END 0x0000d601
7228 #define A6XX_CP_EVENT_END_STATE_ID__MASK 0x000000ff
7229 #define A6XX_CP_EVENT_END_STATE_ID__SHIFT 0
A6XX_CP_EVENT_END_STATE_ID(uint32_t val)7230 static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val)
7231 {
7232 return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK;
7233 }
7234
7235 #define REG_A6XX_CP_2D_EVENT_START 0x0000d700
7236 #define A6XX_CP_2D_EVENT_START_STATE_ID__MASK 0x000000ff
7237 #define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT 0
A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val)7238 static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val)
7239 {
7240 return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK;
7241 }
7242
7243 #define REG_A6XX_CP_2D_EVENT_END 0x0000d701
7244 #define A6XX_CP_2D_EVENT_END_STATE_ID__MASK 0x000000ff
7245 #define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT 0
A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val)7246 static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val)
7247 {
7248 return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK;
7249 }
7250
7251 #define REG_A6XX_TEX_SAMP_0 0x00000000
7252 #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
7253 #define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
7254 #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1
A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val)7255 static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val)
7256 {
7257 return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK;
7258 }
7259 #define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
7260 #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3
A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val)7261 static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val)
7262 {
7263 return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK;
7264 }
7265 #define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
7266 #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5
A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val)7267 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val)
7268 {
7269 return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK;
7270 }
7271 #define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
7272 #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8
A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val)7273 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val)
7274 {
7275 return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK;
7276 }
7277 #define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
7278 #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11
A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val)7279 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val)
7280 {
7281 return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK;
7282 }
7283 #define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
7284 #define A6XX_TEX_SAMP_0_ANISO__SHIFT 14
A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val)7285 static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val)
7286 {
7287 return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK;
7288 }
7289 #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
7290 #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
A6XX_TEX_SAMP_0_LOD_BIAS(float val)7291 static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val)
7292 {
7293 return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK;
7294 }
7295
7296 #define REG_A6XX_TEX_SAMP_1 0x00000001
7297 #define A6XX_TEX_SAMP_1_CLAMPENABLE 0x00000001
7298 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
7299 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)7300 static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
7301 {
7302 return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
7303 }
7304 #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
7305 #define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
7306 #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
7307 #define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
7308 #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
A6XX_TEX_SAMP_1_MAX_LOD(float val)7309 static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val)
7310 {
7311 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK;
7312 }
7313 #define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
7314 #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
A6XX_TEX_SAMP_1_MIN_LOD(float val)7315 static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val)
7316 {
7317 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK;
7318 }
7319
7320 #define REG_A6XX_TEX_SAMP_2 0x00000002
7321 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK 0x00000003
7322 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT 0
A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val)7323 static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val)
7324 {
7325 return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK;
7326 }
7327 #define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020
7328 #define A6XX_TEX_SAMP_2_BCOLOR__MASK 0xffffff80
7329 #define A6XX_TEX_SAMP_2_BCOLOR__SHIFT 7
A6XX_TEX_SAMP_2_BCOLOR(uint32_t val)7330 static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val)
7331 {
7332 return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK;
7333 }
7334
7335 #define REG_A6XX_TEX_SAMP_3 0x00000003
7336
7337 #define REG_A6XX_TEX_CONST_0 0x00000000
7338 #define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
7339 #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0
A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)7340 static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)
7341 {
7342 return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK;
7343 }
7344 #define A6XX_TEX_CONST_0_SRGB 0x00000004
7345 #define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
7346 #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4
A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val)7347 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val)
7348 {
7349 return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK;
7350 }
7351 #define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
7352 #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val)7353 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val)
7354 {
7355 return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK;
7356 }
7357 #define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
7358 #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val)7359 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val)
7360 {
7361 return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK;
7362 }
7363 #define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
7364 #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13
A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val)7365 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val)
7366 {
7367 return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK;
7368 }
7369 #define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
7370 #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16
A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)7371 static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)
7372 {
7373 return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK;
7374 }
7375 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X 0x00010000
7376 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y 0x00040000
7377 #define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000
7378 #define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20
A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)7379 static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
7380 {
7381 return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK;
7382 }
7383 #define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000
7384 #define A6XX_TEX_CONST_0_FMT__SHIFT 22
A6XX_TEX_CONST_0_FMT(enum a6xx_format val)7385 static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val)
7386 {
7387 return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK;
7388 }
7389 #define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000
7390 #define A6XX_TEX_CONST_0_SWAP__SHIFT 30
A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)7391 static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
7392 {
7393 return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK;
7394 }
7395
7396 #define REG_A6XX_TEX_CONST_1 0x00000001
7397 #define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
7398 #define A6XX_TEX_CONST_1_WIDTH__SHIFT 0
A6XX_TEX_CONST_1_WIDTH(uint32_t val)7399 static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val)
7400 {
7401 return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK;
7402 }
7403 #define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
7404 #define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15
A6XX_TEX_CONST_1_HEIGHT(uint32_t val)7405 static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val)
7406 {
7407 return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK;
7408 }
7409
7410 #define REG_A6XX_TEX_CONST_2 0x00000002
7411 #define A6XX_TEX_CONST_2_BUFFER 0x00000010
7412 #define A6XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
7413 #define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val)7414 static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
7415 {
7416 return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK;
7417 }
7418 #define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
7419 #define A6XX_TEX_CONST_2_PITCH__SHIFT 7
A6XX_TEX_CONST_2_PITCH(uint32_t val)7420 static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val)
7421 {
7422 return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK;
7423 }
7424 #define A6XX_TEX_CONST_2_TYPE__MASK 0xe0000000
7425 #define A6XX_TEX_CONST_2_TYPE__SHIFT 29
A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)7426 static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)
7427 {
7428 return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK;
7429 }
7430
7431 #define REG_A6XX_TEX_CONST_3 0x00000003
7432 #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
7433 #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)7434 static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
7435 {
7436 return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK;
7437 }
7438 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000
7439 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23
A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)7440 static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
7441 {
7442 return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
7443 }
7444 #define A6XX_TEX_CONST_3_TILE_ALL 0x08000000
7445 #define A6XX_TEX_CONST_3_FLAG 0x10000000
7446
7447 #define REG_A6XX_TEX_CONST_4 0x00000004
7448 #define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
7449 #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5
A6XX_TEX_CONST_4_BASE_LO(uint32_t val)7450 static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val)
7451 {
7452 return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK;
7453 }
7454
7455 #define REG_A6XX_TEX_CONST_5 0x00000005
7456 #define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
7457 #define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0
A6XX_TEX_CONST_5_BASE_HI(uint32_t val)7458 static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val)
7459 {
7460 return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK;
7461 }
7462 #define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
7463 #define A6XX_TEX_CONST_5_DEPTH__SHIFT 17
A6XX_TEX_CONST_5_DEPTH(uint32_t val)7464 static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val)
7465 {
7466 return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK;
7467 }
7468
7469 #define REG_A6XX_TEX_CONST_6 0x00000006
7470 #define A6XX_TEX_CONST_6_PLANE_PITCH__MASK 0xffffff00
7471 #define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT 8
A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val)7472 static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val)
7473 {
7474 return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK;
7475 }
7476
7477 #define REG_A6XX_TEX_CONST_7 0x00000007
7478 #define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0
7479 #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5
A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)7480 static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)
7481 {
7482 return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK;
7483 }
7484
7485 #define REG_A6XX_TEX_CONST_8 0x00000008
7486 #define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff
7487 #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0
A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)7488 static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)
7489 {
7490 return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK;
7491 }
7492
7493 #define REG_A6XX_TEX_CONST_9 0x00000009
7494 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff
7495 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)7496 static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
7497 {
7498 return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
7499 }
7500
7501 #define REG_A6XX_TEX_CONST_10 0x0000000a
7502 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f
7503 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0
A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val)7504 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val)
7505 {
7506 return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK;
7507 }
7508 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00
7509 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8
A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val)7510 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val)
7511 {
7512 return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK;
7513 }
7514 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK 0x0000f000
7515 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT 12
A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val)7516 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val)
7517 {
7518 return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK;
7519 }
7520
7521 #define REG_A6XX_TEX_CONST_11 0x0000000b
7522
7523 #define REG_A6XX_TEX_CONST_12 0x0000000c
7524
7525 #define REG_A6XX_TEX_CONST_13 0x0000000d
7526
7527 #define REG_A6XX_TEX_CONST_14 0x0000000e
7528
7529 #define REG_A6XX_TEX_CONST_15 0x0000000f
7530
7531 #define REG_A6XX_UBO_0 0x00000000
7532 #define A6XX_UBO_0_BASE_LO__MASK 0xffffffff
7533 #define A6XX_UBO_0_BASE_LO__SHIFT 0
A6XX_UBO_0_BASE_LO(uint32_t val)7534 static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val)
7535 {
7536 return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK;
7537 }
7538
7539 #define REG_A6XX_UBO_1 0x00000001
7540 #define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff
7541 #define A6XX_UBO_1_BASE_HI__SHIFT 0
A6XX_UBO_1_BASE_HI(uint32_t val)7542 static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val)
7543 {
7544 return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK;
7545 }
7546 #define A6XX_UBO_1_SIZE__MASK 0xfffe0000
7547 #define A6XX_UBO_1_SIZE__SHIFT 17
A6XX_UBO_1_SIZE(uint32_t val)7548 static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val)
7549 {
7550 return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK;
7551 }
7552
7553 #define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140
7554
7555 #define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148
7556
7557 #define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540
7558
7559 #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541
7560
7561 #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542
7562
7563 #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543
7564
7565 #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544
7566
7567 #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545
7568
7569 #define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572
7570
7571 #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573
7572
7573 #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574
7574
7575 #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575
7576
7577 #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576
7578
7579 #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577
7580
7581 #define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4
7582
7583 #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5
7584
7585 #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6
7586
7587 #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7
7588
7589 #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8
7590
7591 #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9
7592
7593 #define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6
7594
7595 #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7
7596
7597 #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8
7598
7599 #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9
7600
7601 #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da
7602
7603 #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db
7604
7605 #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000
7606
7607 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000
7608 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff
7609 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0
A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val)7610 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val)
7611 {
7612 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK;
7613 }
7614 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00
7615 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8
A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val)7616 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val)
7617 {
7618 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK;
7619 }
7620
7621 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001
7622
7623 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002
7624
7625 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003
7626
7627 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004
7628 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
7629 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)7630 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
7631 {
7632 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
7633 }
7634 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
7635 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)7636 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
7637 {
7638 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
7639 }
7640 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
7641 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)7642 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
7643 {
7644 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
7645 }
7646
7647 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005
7648 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
7649 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)7650 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
7651 {
7652 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
7653 }
7654
7655 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008
7656
7657 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009
7658
7659 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a
7660
7661 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b
7662
7663 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c
7664
7665 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d
7666
7667 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e
7668
7669 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f
7670
7671 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010
7672 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
7673 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)7674 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
7675 {
7676 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
7677 }
7678 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
7679 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)7680 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
7681 {
7682 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
7683 }
7684 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
7685 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)7686 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
7687 {
7688 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
7689 }
7690 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
7691 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)7692 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
7693 {
7694 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
7695 }
7696 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
7697 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)7698 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
7699 {
7700 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
7701 }
7702 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
7703 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)7704 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
7705 {
7706 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
7707 }
7708 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
7709 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)7710 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
7711 {
7712 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
7713 }
7714 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
7715 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)7716 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
7717 {
7718 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
7719 }
7720
7721 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011
7722 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
7723 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)7724 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
7725 {
7726 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
7727 }
7728 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
7729 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)7730 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
7731 {
7732 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
7733 }
7734 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
7735 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)7736 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
7737 {
7738 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
7739 }
7740 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
7741 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)7742 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
7743 {
7744 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
7745 }
7746 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
7747 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)7748 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
7749 {
7750 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
7751 }
7752 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
7753 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)7754 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
7755 {
7756 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
7757 }
7758 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
7759 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)7760 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
7761 {
7762 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
7763 }
7764 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
7765 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)7766 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
7767 {
7768 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
7769 }
7770
7771 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f
7772
7773 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030
7774
7775 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001
7776
7777 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002
7778
7779
7780 #endif /* A6XX_XML */
7781