1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * R-Car Gen3 Digital Radio Interface (DRIF) driver
4 *
5 * Copyright (C) 2017 Renesas Electronics Corporation
6 */
7
8 /*
9 * The R-Car DRIF is a receive only MSIOF like controller with an
10 * external master device driving the SCK. It receives data into a FIFO,
11 * then this driver uses the SYS-DMAC engine to move the data from
12 * the device to memory.
13 *
14 * Each DRIF channel DRIFx (as per datasheet) contains two internal
15 * channels DRIFx0 & DRIFx1 within itself with each having its own resources
16 * like module clk, register set, irq and dma. These internal channels share
17 * common CLK & SYNC from master. The two data pins D0 & D1 shall be
18 * considered to represent the two internal channels. This internal split
19 * is not visible to the master device.
20 *
21 * Depending on the master device, a DRIF channel can use
22 * (1) both internal channels (D0 & D1) to receive data in parallel (or)
23 * (2) one internal channel (D0 or D1) to receive data
24 *
25 * The primary design goal of this controller is to act as a Digital Radio
26 * Interface that receives digital samples from a tuner device. Hence the
27 * driver exposes the device as a V4L2 SDR device. In order to qualify as
28 * a V4L2 SDR device, it should possess a tuner interface as mandated by the
29 * framework. This driver expects a tuner driver (sub-device) to bind
30 * asynchronously with this device and the combined drivers shall expose
31 * a V4L2 compliant SDR device. The DRIF driver is independent of the
32 * tuner vendor.
33 *
34 * The DRIF h/w can support I2S mode and Frame start synchronization pulse mode.
35 * This driver is tested for I2S mode only because of the availability of
36 * suitable master devices. Hence, not all configurable options of DRIF h/w
37 * like lsb/msb first, syncdl, dtdl etc. are exposed via DT and I2S defaults
38 * are used. These can be exposed later if needed after testing.
39 */
40 #include <linux/bitops.h>
41 #include <linux/clk.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/dmaengine.h>
44 #include <linux/ioctl.h>
45 #include <linux/iopoll.h>
46 #include <linux/module.h>
47 #include <linux/of_graph.h>
48 #include <linux/of_device.h>
49 #include <linux/platform_device.h>
50 #include <linux/sched.h>
51 #include <media/v4l2-async.h>
52 #include <media/v4l2-ctrls.h>
53 #include <media/v4l2-device.h>
54 #include <media/v4l2-event.h>
55 #include <media/v4l2-fh.h>
56 #include <media/v4l2-ioctl.h>
57 #include <media/videobuf2-v4l2.h>
58 #include <media/videobuf2-vmalloc.h>
59
60 /* DRIF register offsets */
61 #define RCAR_DRIF_SITMDR1 0x00
62 #define RCAR_DRIF_SITMDR2 0x04
63 #define RCAR_DRIF_SITMDR3 0x08
64 #define RCAR_DRIF_SIRMDR1 0x10
65 #define RCAR_DRIF_SIRMDR2 0x14
66 #define RCAR_DRIF_SIRMDR3 0x18
67 #define RCAR_DRIF_SICTR 0x28
68 #define RCAR_DRIF_SIFCTR 0x30
69 #define RCAR_DRIF_SISTR 0x40
70 #define RCAR_DRIF_SIIER 0x44
71 #define RCAR_DRIF_SIRFDR 0x60
72
73 #define RCAR_DRIF_RFOVF BIT(3) /* Receive FIFO overflow */
74 #define RCAR_DRIF_RFUDF BIT(4) /* Receive FIFO underflow */
75 #define RCAR_DRIF_RFSERR BIT(5) /* Receive frame sync error */
76 #define RCAR_DRIF_REOF BIT(7) /* Frame reception end */
77 #define RCAR_DRIF_RDREQ BIT(12) /* Receive data xfer req */
78 #define RCAR_DRIF_RFFUL BIT(13) /* Receive FIFO full */
79
80 /* SIRMDR1 */
81 #define RCAR_DRIF_SIRMDR1_SYNCMD_FRAME (0 << 28)
82 #define RCAR_DRIF_SIRMDR1_SYNCMD_LR (3 << 28)
83
84 #define RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH (0 << 25)
85 #define RCAR_DRIF_SIRMDR1_SYNCAC_POL_LOW (1 << 25)
86
87 #define RCAR_DRIF_SIRMDR1_MSB_FIRST (0 << 24)
88 #define RCAR_DRIF_SIRMDR1_LSB_FIRST (1 << 24)
89
90 #define RCAR_DRIF_SIRMDR1_DTDL_0 (0 << 20)
91 #define RCAR_DRIF_SIRMDR1_DTDL_1 (1 << 20)
92 #define RCAR_DRIF_SIRMDR1_DTDL_2 (2 << 20)
93 #define RCAR_DRIF_SIRMDR1_DTDL_0PT5 (5 << 20)
94 #define RCAR_DRIF_SIRMDR1_DTDL_1PT5 (6 << 20)
95
96 #define RCAR_DRIF_SIRMDR1_SYNCDL_0 (0 << 20)
97 #define RCAR_DRIF_SIRMDR1_SYNCDL_1 (1 << 20)
98 #define RCAR_DRIF_SIRMDR1_SYNCDL_2 (2 << 20)
99 #define RCAR_DRIF_SIRMDR1_SYNCDL_3 (3 << 20)
100 #define RCAR_DRIF_SIRMDR1_SYNCDL_0PT5 (5 << 20)
101 #define RCAR_DRIF_SIRMDR1_SYNCDL_1PT5 (6 << 20)
102
103 #define RCAR_DRIF_MDR_GRPCNT(n) (((n) - 1) << 30)
104 #define RCAR_DRIF_MDR_BITLEN(n) (((n) - 1) << 24)
105 #define RCAR_DRIF_MDR_WDCNT(n) (((n) - 1) << 16)
106
107 /* Hidden Transmit register that controls CLK & SYNC */
108 #define RCAR_DRIF_SITMDR1_PCON BIT(30)
109
110 #define RCAR_DRIF_SICTR_RX_RISING_EDGE BIT(26)
111 #define RCAR_DRIF_SICTR_RX_EN BIT(8)
112 #define RCAR_DRIF_SICTR_RESET BIT(0)
113
114 /* Constants */
115 #define RCAR_DRIF_NUM_HWBUFS 32
116 #define RCAR_DRIF_MAX_DEVS 4
117 #define RCAR_DRIF_DEFAULT_NUM_HWBUFS 16
118 #define RCAR_DRIF_DEFAULT_HWBUF_SIZE (4 * PAGE_SIZE)
119 #define RCAR_DRIF_MAX_CHANNEL 2
120 #define RCAR_SDR_BUFFER_SIZE SZ_64K
121
122 /* Internal buffer status flags */
123 #define RCAR_DRIF_BUF_DONE BIT(0) /* DMA completed */
124 #define RCAR_DRIF_BUF_OVERFLOW BIT(1) /* Overflow detected */
125
126 #define to_rcar_drif_buf_pair(sdr, ch_num, idx) \
127 (&((sdr)->ch[!(ch_num)]->buf[(idx)]))
128
129 #define for_each_rcar_drif_channel(ch, ch_mask) \
130 for_each_set_bit(ch, ch_mask, RCAR_DRIF_MAX_CHANNEL)
131
132 /* Debug */
133 #define rdrif_dbg(sdr, fmt, arg...) \
134 dev_dbg(sdr->v4l2_dev.dev, fmt, ## arg)
135
136 #define rdrif_err(sdr, fmt, arg...) \
137 dev_err(sdr->v4l2_dev.dev, fmt, ## arg)
138
139 /* Stream formats */
140 struct rcar_drif_format {
141 u32 pixelformat;
142 u32 buffersize;
143 u32 bitlen;
144 u32 wdcnt;
145 u32 num_ch;
146 };
147
148 /* Format descriptions for capture */
149 static const struct rcar_drif_format formats[] = {
150 {
151 .pixelformat = V4L2_SDR_FMT_PCU16BE,
152 .buffersize = RCAR_SDR_BUFFER_SIZE,
153 .bitlen = 16,
154 .wdcnt = 1,
155 .num_ch = 2,
156 },
157 {
158 .pixelformat = V4L2_SDR_FMT_PCU18BE,
159 .buffersize = RCAR_SDR_BUFFER_SIZE,
160 .bitlen = 18,
161 .wdcnt = 1,
162 .num_ch = 2,
163 },
164 {
165 .pixelformat = V4L2_SDR_FMT_PCU20BE,
166 .buffersize = RCAR_SDR_BUFFER_SIZE,
167 .bitlen = 20,
168 .wdcnt = 1,
169 .num_ch = 2,
170 },
171 };
172
173 /* Buffer for a received frame from one or both internal channels */
174 struct rcar_drif_frame_buf {
175 /* Common v4l buffer stuff -- must be first */
176 struct vb2_v4l2_buffer vb;
177 struct list_head list;
178 };
179
180 /* OF graph endpoint's V4L2 async data */
181 struct rcar_drif_graph_ep {
182 struct v4l2_subdev *subdev; /* Async matched subdev */
183 };
184
185 /* DMA buffer */
186 struct rcar_drif_hwbuf {
187 void *addr; /* CPU-side address */
188 unsigned int status; /* Buffer status flags */
189 };
190
191 /* Internal channel */
192 struct rcar_drif {
193 struct rcar_drif_sdr *sdr; /* Group device */
194 struct platform_device *pdev; /* Channel's pdev */
195 void __iomem *base; /* Base register address */
196 resource_size_t start; /* I/O resource offset */
197 struct dma_chan *dmach; /* Reserved DMA channel */
198 struct clk *clk; /* Module clock */
199 struct rcar_drif_hwbuf buf[RCAR_DRIF_NUM_HWBUFS]; /* H/W bufs */
200 dma_addr_t dma_handle; /* Handle for all bufs */
201 unsigned int num; /* Channel number */
202 bool acting_sdr; /* Channel acting as SDR device */
203 };
204
205 /* DRIF V4L2 SDR */
206 struct rcar_drif_sdr {
207 struct device *dev; /* Platform device */
208 struct video_device *vdev; /* V4L2 SDR device */
209 struct v4l2_device v4l2_dev; /* V4L2 device */
210
211 /* Videobuf2 queue and queued buffers list */
212 struct vb2_queue vb_queue;
213 struct list_head queued_bufs;
214 spinlock_t queued_bufs_lock; /* Protects queued_bufs */
215 spinlock_t dma_lock; /* To serialize DMA cb of channels */
216
217 struct mutex v4l2_mutex; /* To serialize ioctls */
218 struct mutex vb_queue_mutex; /* To serialize streaming ioctls */
219 struct v4l2_ctrl_handler ctrl_hdl; /* SDR control handler */
220 struct v4l2_async_notifier notifier; /* For subdev (tuner) */
221 struct rcar_drif_graph_ep ep; /* Endpoint V4L2 async data */
222
223 /* Current V4L2 SDR format ptr */
224 const struct rcar_drif_format *fmt;
225
226 /* Device tree SYNC properties */
227 u32 mdr1;
228
229 /* Internals */
230 struct rcar_drif *ch[RCAR_DRIF_MAX_CHANNEL]; /* DRIFx0,1 */
231 unsigned long hw_ch_mask; /* Enabled channels per DT */
232 unsigned long cur_ch_mask; /* Used channels for an SDR FMT */
233 u32 num_hw_ch; /* Num of DT enabled channels */
234 u32 num_cur_ch; /* Num of used channels */
235 u32 hwbuf_size; /* Each DMA buffer size */
236 u32 produced; /* Buffers produced by sdr dev */
237 };
238
239 /* Register access functions */
rcar_drif_write(struct rcar_drif * ch,u32 offset,u32 data)240 static void rcar_drif_write(struct rcar_drif *ch, u32 offset, u32 data)
241 {
242 writel(data, ch->base + offset);
243 }
244
rcar_drif_read(struct rcar_drif * ch,u32 offset)245 static u32 rcar_drif_read(struct rcar_drif *ch, u32 offset)
246 {
247 return readl(ch->base + offset);
248 }
249
250 /* Release DMA channels */
rcar_drif_release_dmachannels(struct rcar_drif_sdr * sdr)251 static void rcar_drif_release_dmachannels(struct rcar_drif_sdr *sdr)
252 {
253 unsigned int i;
254
255 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask)
256 if (sdr->ch[i]->dmach) {
257 dma_release_channel(sdr->ch[i]->dmach);
258 sdr->ch[i]->dmach = NULL;
259 }
260 }
261
262 /* Allocate DMA channels */
rcar_drif_alloc_dmachannels(struct rcar_drif_sdr * sdr)263 static int rcar_drif_alloc_dmachannels(struct rcar_drif_sdr *sdr)
264 {
265 struct dma_slave_config dma_cfg;
266 unsigned int i;
267 int ret;
268
269 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
270 struct rcar_drif *ch = sdr->ch[i];
271
272 ch->dmach = dma_request_chan(&ch->pdev->dev, "rx");
273 if (IS_ERR(ch->dmach)) {
274 ret = PTR_ERR(ch->dmach);
275 if (ret != -EPROBE_DEFER)
276 rdrif_err(sdr,
277 "ch%u: dma channel req failed: %pe\n",
278 i, ch->dmach);
279 ch->dmach = NULL;
280 goto dmach_error;
281 }
282
283 /* Configure slave */
284 memset(&dma_cfg, 0, sizeof(dma_cfg));
285 dma_cfg.src_addr = (phys_addr_t)(ch->start + RCAR_DRIF_SIRFDR);
286 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
287 ret = dmaengine_slave_config(ch->dmach, &dma_cfg);
288 if (ret) {
289 rdrif_err(sdr, "ch%u: dma slave config failed\n", i);
290 goto dmach_error;
291 }
292 }
293 return 0;
294
295 dmach_error:
296 rcar_drif_release_dmachannels(sdr);
297 return ret;
298 }
299
300 /* Release queued vb2 buffers */
rcar_drif_release_queued_bufs(struct rcar_drif_sdr * sdr,enum vb2_buffer_state state)301 static void rcar_drif_release_queued_bufs(struct rcar_drif_sdr *sdr,
302 enum vb2_buffer_state state)
303 {
304 struct rcar_drif_frame_buf *fbuf, *tmp;
305 unsigned long flags;
306
307 spin_lock_irqsave(&sdr->queued_bufs_lock, flags);
308 list_for_each_entry_safe(fbuf, tmp, &sdr->queued_bufs, list) {
309 list_del(&fbuf->list);
310 vb2_buffer_done(&fbuf->vb.vb2_buf, state);
311 }
312 spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
313 }
314
315 /* Set MDR defaults */
rcar_drif_set_mdr1(struct rcar_drif_sdr * sdr)316 static inline void rcar_drif_set_mdr1(struct rcar_drif_sdr *sdr)
317 {
318 unsigned int i;
319
320 /* Set defaults for enabled internal channels */
321 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
322 /* Refer MSIOF section in manual for this register setting */
323 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SITMDR1,
324 RCAR_DRIF_SITMDR1_PCON);
325
326 /* Setup MDR1 value */
327 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR1, sdr->mdr1);
328
329 rdrif_dbg(sdr, "ch%u: mdr1 = 0x%08x",
330 i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR1));
331 }
332 }
333
334 /* Set DRIF receive format */
rcar_drif_set_format(struct rcar_drif_sdr * sdr)335 static int rcar_drif_set_format(struct rcar_drif_sdr *sdr)
336 {
337 unsigned int i;
338
339 rdrif_dbg(sdr, "setfmt: bitlen %u wdcnt %u num_ch %u\n",
340 sdr->fmt->bitlen, sdr->fmt->wdcnt, sdr->fmt->num_ch);
341
342 /* Sanity check */
343 if (sdr->fmt->num_ch > sdr->num_cur_ch) {
344 rdrif_err(sdr, "fmt num_ch %u cur_ch %u mismatch\n",
345 sdr->fmt->num_ch, sdr->num_cur_ch);
346 return -EINVAL;
347 }
348
349 /* Setup group, bitlen & wdcnt */
350 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
351 u32 mdr;
352
353 /* Two groups */
354 mdr = RCAR_DRIF_MDR_GRPCNT(2) |
355 RCAR_DRIF_MDR_BITLEN(sdr->fmt->bitlen) |
356 RCAR_DRIF_MDR_WDCNT(sdr->fmt->wdcnt);
357 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR2, mdr);
358
359 mdr = RCAR_DRIF_MDR_BITLEN(sdr->fmt->bitlen) |
360 RCAR_DRIF_MDR_WDCNT(sdr->fmt->wdcnt);
361 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR3, mdr);
362
363 rdrif_dbg(sdr, "ch%u: new mdr[2,3] = 0x%08x, 0x%08x\n",
364 i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR2),
365 rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR3));
366 }
367 return 0;
368 }
369
370 /* Release DMA buffers */
rcar_drif_release_buf(struct rcar_drif_sdr * sdr)371 static void rcar_drif_release_buf(struct rcar_drif_sdr *sdr)
372 {
373 unsigned int i;
374
375 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
376 struct rcar_drif *ch = sdr->ch[i];
377
378 /* First entry contains the dma buf ptr */
379 if (ch->buf[0].addr) {
380 dma_free_coherent(&ch->pdev->dev,
381 sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS,
382 ch->buf[0].addr, ch->dma_handle);
383 ch->buf[0].addr = NULL;
384 }
385 }
386 }
387
388 /* Request DMA buffers */
rcar_drif_request_buf(struct rcar_drif_sdr * sdr)389 static int rcar_drif_request_buf(struct rcar_drif_sdr *sdr)
390 {
391 int ret = -ENOMEM;
392 unsigned int i, j;
393 void *addr;
394
395 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
396 struct rcar_drif *ch = sdr->ch[i];
397
398 /* Allocate DMA buffers */
399 addr = dma_alloc_coherent(&ch->pdev->dev,
400 sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS,
401 &ch->dma_handle, GFP_KERNEL);
402 if (!addr) {
403 rdrif_err(sdr,
404 "ch%u: dma alloc failed. num hwbufs %u size %u\n",
405 i, RCAR_DRIF_NUM_HWBUFS, sdr->hwbuf_size);
406 goto error;
407 }
408
409 /* Split the chunk and populate bufctxt */
410 for (j = 0; j < RCAR_DRIF_NUM_HWBUFS; j++) {
411 ch->buf[j].addr = addr + (j * sdr->hwbuf_size);
412 ch->buf[j].status = 0;
413 }
414 }
415 return 0;
416 error:
417 return ret;
418 }
419
420 /* Setup vb_queue minimum buffer requirements */
rcar_drif_queue_setup(struct vb2_queue * vq,unsigned int * num_buffers,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_devs[])421 static int rcar_drif_queue_setup(struct vb2_queue *vq,
422 unsigned int *num_buffers, unsigned int *num_planes,
423 unsigned int sizes[], struct device *alloc_devs[])
424 {
425 struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq);
426
427 /* Need at least 16 buffers */
428 if (vq->num_buffers + *num_buffers < 16)
429 *num_buffers = 16 - vq->num_buffers;
430
431 *num_planes = 1;
432 sizes[0] = PAGE_ALIGN(sdr->fmt->buffersize);
433 rdrif_dbg(sdr, "num_bufs %d sizes[0] %d\n", *num_buffers, sizes[0]);
434
435 return 0;
436 }
437
438 /* Enqueue buffer */
rcar_drif_buf_queue(struct vb2_buffer * vb)439 static void rcar_drif_buf_queue(struct vb2_buffer *vb)
440 {
441 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
442 struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vb->vb2_queue);
443 struct rcar_drif_frame_buf *fbuf =
444 container_of(vbuf, struct rcar_drif_frame_buf, vb);
445 unsigned long flags;
446
447 rdrif_dbg(sdr, "buf_queue idx %u\n", vb->index);
448 spin_lock_irqsave(&sdr->queued_bufs_lock, flags);
449 list_add_tail(&fbuf->list, &sdr->queued_bufs);
450 spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
451 }
452
453 /* Get a frame buf from list */
454 static struct rcar_drif_frame_buf *
rcar_drif_get_fbuf(struct rcar_drif_sdr * sdr)455 rcar_drif_get_fbuf(struct rcar_drif_sdr *sdr)
456 {
457 struct rcar_drif_frame_buf *fbuf;
458 unsigned long flags;
459
460 spin_lock_irqsave(&sdr->queued_bufs_lock, flags);
461 fbuf = list_first_entry_or_null(&sdr->queued_bufs, struct
462 rcar_drif_frame_buf, list);
463 if (!fbuf) {
464 /*
465 * App is late in enqueing buffers. Samples lost & there will
466 * be a gap in sequence number when app recovers
467 */
468 rdrif_dbg(sdr, "\napp late: prod %u\n", sdr->produced);
469 spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
470 return NULL;
471 }
472 list_del(&fbuf->list);
473 spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
474
475 return fbuf;
476 }
477
478 /* Helpers to set/clear buf pair status */
rcar_drif_bufs_done(struct rcar_drif_hwbuf ** buf)479 static inline bool rcar_drif_bufs_done(struct rcar_drif_hwbuf **buf)
480 {
481 return (buf[0]->status & buf[1]->status & RCAR_DRIF_BUF_DONE);
482 }
483
rcar_drif_bufs_overflow(struct rcar_drif_hwbuf ** buf)484 static inline bool rcar_drif_bufs_overflow(struct rcar_drif_hwbuf **buf)
485 {
486 return ((buf[0]->status | buf[1]->status) & RCAR_DRIF_BUF_OVERFLOW);
487 }
488
rcar_drif_bufs_clear(struct rcar_drif_hwbuf ** buf,unsigned int bit)489 static inline void rcar_drif_bufs_clear(struct rcar_drif_hwbuf **buf,
490 unsigned int bit)
491 {
492 unsigned int i;
493
494 for (i = 0; i < RCAR_DRIF_MAX_CHANNEL; i++)
495 buf[i]->status &= ~bit;
496 }
497
498 /* Channel DMA complete */
rcar_drif_channel_complete(struct rcar_drif * ch,u32 idx)499 static void rcar_drif_channel_complete(struct rcar_drif *ch, u32 idx)
500 {
501 u32 str;
502
503 ch->buf[idx].status |= RCAR_DRIF_BUF_DONE;
504
505 /* Check for DRIF errors */
506 str = rcar_drif_read(ch, RCAR_DRIF_SISTR);
507 if (unlikely(str & RCAR_DRIF_RFOVF)) {
508 /* Writing the same clears it */
509 rcar_drif_write(ch, RCAR_DRIF_SISTR, str);
510
511 /* Overflow: some samples are lost */
512 ch->buf[idx].status |= RCAR_DRIF_BUF_OVERFLOW;
513 }
514 }
515
516 /* DMA callback for each stage */
rcar_drif_dma_complete(void * dma_async_param)517 static void rcar_drif_dma_complete(void *dma_async_param)
518 {
519 struct rcar_drif *ch = dma_async_param;
520 struct rcar_drif_sdr *sdr = ch->sdr;
521 struct rcar_drif_hwbuf *buf[RCAR_DRIF_MAX_CHANNEL];
522 struct rcar_drif_frame_buf *fbuf;
523 bool overflow = false;
524 u32 idx, produced;
525 unsigned int i;
526
527 spin_lock(&sdr->dma_lock);
528
529 /* DMA can be terminated while the callback was waiting on lock */
530 if (!vb2_is_streaming(&sdr->vb_queue)) {
531 spin_unlock(&sdr->dma_lock);
532 return;
533 }
534
535 idx = sdr->produced % RCAR_DRIF_NUM_HWBUFS;
536 rcar_drif_channel_complete(ch, idx);
537
538 if (sdr->num_cur_ch == RCAR_DRIF_MAX_CHANNEL) {
539 buf[0] = ch->num ? to_rcar_drif_buf_pair(sdr, ch->num, idx) :
540 &ch->buf[idx];
541 buf[1] = ch->num ? &ch->buf[idx] :
542 to_rcar_drif_buf_pair(sdr, ch->num, idx);
543
544 /* Check if both DMA buffers are done */
545 if (!rcar_drif_bufs_done(buf)) {
546 spin_unlock(&sdr->dma_lock);
547 return;
548 }
549
550 /* Clear buf done status */
551 rcar_drif_bufs_clear(buf, RCAR_DRIF_BUF_DONE);
552
553 if (rcar_drif_bufs_overflow(buf)) {
554 overflow = true;
555 /* Clear the flag in status */
556 rcar_drif_bufs_clear(buf, RCAR_DRIF_BUF_OVERFLOW);
557 }
558 } else {
559 buf[0] = &ch->buf[idx];
560 if (buf[0]->status & RCAR_DRIF_BUF_OVERFLOW) {
561 overflow = true;
562 /* Clear the flag in status */
563 buf[0]->status &= ~RCAR_DRIF_BUF_OVERFLOW;
564 }
565 }
566
567 /* Buffer produced for consumption */
568 produced = sdr->produced++;
569 spin_unlock(&sdr->dma_lock);
570
571 rdrif_dbg(sdr, "ch%u: prod %u\n", ch->num, produced);
572
573 /* Get fbuf */
574 fbuf = rcar_drif_get_fbuf(sdr);
575 if (!fbuf)
576 return;
577
578 for (i = 0; i < RCAR_DRIF_MAX_CHANNEL; i++)
579 memcpy(vb2_plane_vaddr(&fbuf->vb.vb2_buf, 0) +
580 i * sdr->hwbuf_size, buf[i]->addr, sdr->hwbuf_size);
581
582 fbuf->vb.field = V4L2_FIELD_NONE;
583 fbuf->vb.sequence = produced;
584 fbuf->vb.vb2_buf.timestamp = ktime_get_ns();
585 vb2_set_plane_payload(&fbuf->vb.vb2_buf, 0, sdr->fmt->buffersize);
586
587 /* Set error state on overflow */
588 vb2_buffer_done(&fbuf->vb.vb2_buf,
589 overflow ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
590 }
591
rcar_drif_qbuf(struct rcar_drif * ch)592 static int rcar_drif_qbuf(struct rcar_drif *ch)
593 {
594 struct rcar_drif_sdr *sdr = ch->sdr;
595 dma_addr_t addr = ch->dma_handle;
596 struct dma_async_tx_descriptor *rxd;
597 dma_cookie_t cookie;
598 int ret = -EIO;
599
600 /* Setup cyclic DMA with given buffers */
601 rxd = dmaengine_prep_dma_cyclic(ch->dmach, addr,
602 sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS,
603 sdr->hwbuf_size, DMA_DEV_TO_MEM,
604 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
605 if (!rxd) {
606 rdrif_err(sdr, "ch%u: prep dma cyclic failed\n", ch->num);
607 return ret;
608 }
609
610 /* Submit descriptor */
611 rxd->callback = rcar_drif_dma_complete;
612 rxd->callback_param = ch;
613 cookie = dmaengine_submit(rxd);
614 if (dma_submit_error(cookie)) {
615 rdrif_err(sdr, "ch%u: dma submit failed\n", ch->num);
616 return ret;
617 }
618
619 dma_async_issue_pending(ch->dmach);
620 return 0;
621 }
622
623 /* Enable reception */
rcar_drif_enable_rx(struct rcar_drif_sdr * sdr)624 static int rcar_drif_enable_rx(struct rcar_drif_sdr *sdr)
625 {
626 unsigned int i;
627 u32 ctr;
628 int ret = -EINVAL;
629
630 /*
631 * When both internal channels are enabled, they can be synchronized
632 * only by the master
633 */
634
635 /* Enable receive */
636 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
637 ctr = rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR);
638 ctr |= (RCAR_DRIF_SICTR_RX_RISING_EDGE |
639 RCAR_DRIF_SICTR_RX_EN);
640 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SICTR, ctr);
641 }
642
643 /* Check receive enabled */
644 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
645 ret = readl_poll_timeout(sdr->ch[i]->base + RCAR_DRIF_SICTR,
646 ctr, ctr & RCAR_DRIF_SICTR_RX_EN, 7, 100000);
647 if (ret) {
648 rdrif_err(sdr, "ch%u: rx en failed. ctr 0x%08x\n", i,
649 rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR));
650 break;
651 }
652 }
653 return ret;
654 }
655
656 /* Disable reception */
rcar_drif_disable_rx(struct rcar_drif_sdr * sdr)657 static void rcar_drif_disable_rx(struct rcar_drif_sdr *sdr)
658 {
659 unsigned int i;
660 u32 ctr;
661 int ret;
662
663 /* Disable receive */
664 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
665 ctr = rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR);
666 ctr &= ~RCAR_DRIF_SICTR_RX_EN;
667 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SICTR, ctr);
668 }
669
670 /* Check receive disabled */
671 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
672 ret = readl_poll_timeout(sdr->ch[i]->base + RCAR_DRIF_SICTR,
673 ctr, !(ctr & RCAR_DRIF_SICTR_RX_EN), 7, 100000);
674 if (ret)
675 dev_warn(&sdr->vdev->dev,
676 "ch%u: failed to disable rx. ctr 0x%08x\n",
677 i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR));
678 }
679 }
680
681 /* Stop channel */
rcar_drif_stop_channel(struct rcar_drif * ch)682 static void rcar_drif_stop_channel(struct rcar_drif *ch)
683 {
684 /* Disable DMA receive interrupt */
685 rcar_drif_write(ch, RCAR_DRIF_SIIER, 0x00000000);
686
687 /* Terminate all DMA transfers */
688 dmaengine_terminate_sync(ch->dmach);
689 }
690
691 /* Stop receive operation */
rcar_drif_stop(struct rcar_drif_sdr * sdr)692 static void rcar_drif_stop(struct rcar_drif_sdr *sdr)
693 {
694 unsigned int i;
695
696 /* Disable Rx */
697 rcar_drif_disable_rx(sdr);
698
699 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask)
700 rcar_drif_stop_channel(sdr->ch[i]);
701 }
702
703 /* Start channel */
rcar_drif_start_channel(struct rcar_drif * ch)704 static int rcar_drif_start_channel(struct rcar_drif *ch)
705 {
706 struct rcar_drif_sdr *sdr = ch->sdr;
707 u32 ctr, str;
708 int ret;
709
710 /* Reset receive */
711 rcar_drif_write(ch, RCAR_DRIF_SICTR, RCAR_DRIF_SICTR_RESET);
712 ret = readl_poll_timeout(ch->base + RCAR_DRIF_SICTR, ctr,
713 !(ctr & RCAR_DRIF_SICTR_RESET), 7, 100000);
714 if (ret) {
715 rdrif_err(sdr, "ch%u: failed to reset rx. ctr 0x%08x\n",
716 ch->num, rcar_drif_read(ch, RCAR_DRIF_SICTR));
717 return ret;
718 }
719
720 /* Queue buffers for DMA */
721 ret = rcar_drif_qbuf(ch);
722 if (ret)
723 return ret;
724
725 /* Clear status register flags */
726 str = RCAR_DRIF_RFFUL | RCAR_DRIF_REOF | RCAR_DRIF_RFSERR |
727 RCAR_DRIF_RFUDF | RCAR_DRIF_RFOVF;
728 rcar_drif_write(ch, RCAR_DRIF_SISTR, str);
729
730 /* Enable DMA receive interrupt */
731 rcar_drif_write(ch, RCAR_DRIF_SIIER, 0x00009000);
732
733 return ret;
734 }
735
736 /* Start receive operation */
rcar_drif_start(struct rcar_drif_sdr * sdr)737 static int rcar_drif_start(struct rcar_drif_sdr *sdr)
738 {
739 unsigned long enabled = 0;
740 unsigned int i;
741 int ret;
742
743 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
744 ret = rcar_drif_start_channel(sdr->ch[i]);
745 if (ret)
746 goto start_error;
747 enabled |= BIT(i);
748 }
749
750 ret = rcar_drif_enable_rx(sdr);
751 if (ret)
752 goto enable_error;
753
754 sdr->produced = 0;
755 return ret;
756
757 enable_error:
758 rcar_drif_disable_rx(sdr);
759 start_error:
760 for_each_rcar_drif_channel(i, &enabled)
761 rcar_drif_stop_channel(sdr->ch[i]);
762
763 return ret;
764 }
765
766 /* Start streaming */
rcar_drif_start_streaming(struct vb2_queue * vq,unsigned int count)767 static int rcar_drif_start_streaming(struct vb2_queue *vq, unsigned int count)
768 {
769 struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq);
770 unsigned long enabled = 0;
771 unsigned int i;
772 int ret;
773
774 mutex_lock(&sdr->v4l2_mutex);
775
776 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
777 ret = clk_prepare_enable(sdr->ch[i]->clk);
778 if (ret)
779 goto error;
780 enabled |= BIT(i);
781 }
782
783 /* Set default MDRx settings */
784 rcar_drif_set_mdr1(sdr);
785
786 /* Set new format */
787 ret = rcar_drif_set_format(sdr);
788 if (ret)
789 goto error;
790
791 if (sdr->num_cur_ch == RCAR_DRIF_MAX_CHANNEL)
792 sdr->hwbuf_size = sdr->fmt->buffersize / RCAR_DRIF_MAX_CHANNEL;
793 else
794 sdr->hwbuf_size = sdr->fmt->buffersize;
795
796 rdrif_dbg(sdr, "num hwbufs %u, hwbuf_size %u\n",
797 RCAR_DRIF_NUM_HWBUFS, sdr->hwbuf_size);
798
799 /* Alloc DMA channel */
800 ret = rcar_drif_alloc_dmachannels(sdr);
801 if (ret)
802 goto error;
803
804 /* Request buffers */
805 ret = rcar_drif_request_buf(sdr);
806 if (ret)
807 goto error;
808
809 /* Start Rx */
810 ret = rcar_drif_start(sdr);
811 if (ret)
812 goto error;
813
814 mutex_unlock(&sdr->v4l2_mutex);
815
816 return ret;
817
818 error:
819 rcar_drif_release_queued_bufs(sdr, VB2_BUF_STATE_QUEUED);
820 rcar_drif_release_buf(sdr);
821 rcar_drif_release_dmachannels(sdr);
822 for_each_rcar_drif_channel(i, &enabled)
823 clk_disable_unprepare(sdr->ch[i]->clk);
824
825 mutex_unlock(&sdr->v4l2_mutex);
826
827 return ret;
828 }
829
830 /* Stop streaming */
rcar_drif_stop_streaming(struct vb2_queue * vq)831 static void rcar_drif_stop_streaming(struct vb2_queue *vq)
832 {
833 struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq);
834 unsigned int i;
835
836 mutex_lock(&sdr->v4l2_mutex);
837
838 /* Stop hardware streaming */
839 rcar_drif_stop(sdr);
840
841 /* Return all queued buffers to vb2 */
842 rcar_drif_release_queued_bufs(sdr, VB2_BUF_STATE_ERROR);
843
844 /* Release buf */
845 rcar_drif_release_buf(sdr);
846
847 /* Release DMA channel resources */
848 rcar_drif_release_dmachannels(sdr);
849
850 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask)
851 clk_disable_unprepare(sdr->ch[i]->clk);
852
853 mutex_unlock(&sdr->v4l2_mutex);
854 }
855
856 /* Vb2 ops */
857 static const struct vb2_ops rcar_drif_vb2_ops = {
858 .queue_setup = rcar_drif_queue_setup,
859 .buf_queue = rcar_drif_buf_queue,
860 .start_streaming = rcar_drif_start_streaming,
861 .stop_streaming = rcar_drif_stop_streaming,
862 .wait_prepare = vb2_ops_wait_prepare,
863 .wait_finish = vb2_ops_wait_finish,
864 };
865
rcar_drif_querycap(struct file * file,void * fh,struct v4l2_capability * cap)866 static int rcar_drif_querycap(struct file *file, void *fh,
867 struct v4l2_capability *cap)
868 {
869 struct rcar_drif_sdr *sdr = video_drvdata(file);
870
871 strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver));
872 strscpy(cap->card, sdr->vdev->name, sizeof(cap->card));
873 snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
874 sdr->vdev->name);
875
876 return 0;
877 }
878
rcar_drif_set_default_format(struct rcar_drif_sdr * sdr)879 static int rcar_drif_set_default_format(struct rcar_drif_sdr *sdr)
880 {
881 unsigned int i;
882
883 for (i = 0; i < ARRAY_SIZE(formats); i++) {
884 /* Matching fmt based on required channels is set as default */
885 if (sdr->num_hw_ch == formats[i].num_ch) {
886 sdr->fmt = &formats[i];
887 sdr->cur_ch_mask = sdr->hw_ch_mask;
888 sdr->num_cur_ch = sdr->num_hw_ch;
889 dev_dbg(sdr->dev, "default fmt[%u]: mask %lu num %u\n",
890 i, sdr->cur_ch_mask, sdr->num_cur_ch);
891 return 0;
892 }
893 }
894 return -EINVAL;
895 }
896
rcar_drif_enum_fmt_sdr_cap(struct file * file,void * priv,struct v4l2_fmtdesc * f)897 static int rcar_drif_enum_fmt_sdr_cap(struct file *file, void *priv,
898 struct v4l2_fmtdesc *f)
899 {
900 if (f->index >= ARRAY_SIZE(formats))
901 return -EINVAL;
902
903 f->pixelformat = formats[f->index].pixelformat;
904
905 return 0;
906 }
907
rcar_drif_g_fmt_sdr_cap(struct file * file,void * priv,struct v4l2_format * f)908 static int rcar_drif_g_fmt_sdr_cap(struct file *file, void *priv,
909 struct v4l2_format *f)
910 {
911 struct rcar_drif_sdr *sdr = video_drvdata(file);
912
913 f->fmt.sdr.pixelformat = sdr->fmt->pixelformat;
914 f->fmt.sdr.buffersize = sdr->fmt->buffersize;
915
916 return 0;
917 }
918
rcar_drif_s_fmt_sdr_cap(struct file * file,void * priv,struct v4l2_format * f)919 static int rcar_drif_s_fmt_sdr_cap(struct file *file, void *priv,
920 struct v4l2_format *f)
921 {
922 struct rcar_drif_sdr *sdr = video_drvdata(file);
923 struct vb2_queue *q = &sdr->vb_queue;
924 unsigned int i;
925
926 if (vb2_is_busy(q))
927 return -EBUSY;
928
929 for (i = 0; i < ARRAY_SIZE(formats); i++) {
930 if (formats[i].pixelformat == f->fmt.sdr.pixelformat)
931 break;
932 }
933
934 if (i == ARRAY_SIZE(formats))
935 i = 0; /* Set the 1st format as default on no match */
936
937 sdr->fmt = &formats[i];
938 f->fmt.sdr.pixelformat = sdr->fmt->pixelformat;
939 f->fmt.sdr.buffersize = formats[i].buffersize;
940 memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved));
941
942 /*
943 * If a format demands one channel only out of two
944 * enabled channels, pick the 0th channel.
945 */
946 if (formats[i].num_ch < sdr->num_hw_ch) {
947 sdr->cur_ch_mask = BIT(0);
948 sdr->num_cur_ch = formats[i].num_ch;
949 } else {
950 sdr->cur_ch_mask = sdr->hw_ch_mask;
951 sdr->num_cur_ch = sdr->num_hw_ch;
952 }
953
954 rdrif_dbg(sdr, "cur: idx %u mask %lu num %u\n",
955 i, sdr->cur_ch_mask, sdr->num_cur_ch);
956
957 return 0;
958 }
959
rcar_drif_try_fmt_sdr_cap(struct file * file,void * priv,struct v4l2_format * f)960 static int rcar_drif_try_fmt_sdr_cap(struct file *file, void *priv,
961 struct v4l2_format *f)
962 {
963 unsigned int i;
964
965 for (i = 0; i < ARRAY_SIZE(formats); i++) {
966 if (formats[i].pixelformat == f->fmt.sdr.pixelformat) {
967 f->fmt.sdr.buffersize = formats[i].buffersize;
968 return 0;
969 }
970 }
971
972 f->fmt.sdr.pixelformat = formats[0].pixelformat;
973 f->fmt.sdr.buffersize = formats[0].buffersize;
974 memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved));
975
976 return 0;
977 }
978
979 /* Tuner subdev ioctls */
rcar_drif_enum_freq_bands(struct file * file,void * priv,struct v4l2_frequency_band * band)980 static int rcar_drif_enum_freq_bands(struct file *file, void *priv,
981 struct v4l2_frequency_band *band)
982 {
983 struct rcar_drif_sdr *sdr = video_drvdata(file);
984
985 return v4l2_subdev_call(sdr->ep.subdev, tuner, enum_freq_bands, band);
986 }
987
rcar_drif_g_frequency(struct file * file,void * priv,struct v4l2_frequency * f)988 static int rcar_drif_g_frequency(struct file *file, void *priv,
989 struct v4l2_frequency *f)
990 {
991 struct rcar_drif_sdr *sdr = video_drvdata(file);
992
993 return v4l2_subdev_call(sdr->ep.subdev, tuner, g_frequency, f);
994 }
995
rcar_drif_s_frequency(struct file * file,void * priv,const struct v4l2_frequency * f)996 static int rcar_drif_s_frequency(struct file *file, void *priv,
997 const struct v4l2_frequency *f)
998 {
999 struct rcar_drif_sdr *sdr = video_drvdata(file);
1000
1001 return v4l2_subdev_call(sdr->ep.subdev, tuner, s_frequency, f);
1002 }
1003
rcar_drif_g_tuner(struct file * file,void * priv,struct v4l2_tuner * vt)1004 static int rcar_drif_g_tuner(struct file *file, void *priv,
1005 struct v4l2_tuner *vt)
1006 {
1007 struct rcar_drif_sdr *sdr = video_drvdata(file);
1008
1009 return v4l2_subdev_call(sdr->ep.subdev, tuner, g_tuner, vt);
1010 }
1011
rcar_drif_s_tuner(struct file * file,void * priv,const struct v4l2_tuner * vt)1012 static int rcar_drif_s_tuner(struct file *file, void *priv,
1013 const struct v4l2_tuner *vt)
1014 {
1015 struct rcar_drif_sdr *sdr = video_drvdata(file);
1016
1017 return v4l2_subdev_call(sdr->ep.subdev, tuner, s_tuner, vt);
1018 }
1019
1020 static const struct v4l2_ioctl_ops rcar_drif_ioctl_ops = {
1021 .vidioc_querycap = rcar_drif_querycap,
1022
1023 .vidioc_enum_fmt_sdr_cap = rcar_drif_enum_fmt_sdr_cap,
1024 .vidioc_g_fmt_sdr_cap = rcar_drif_g_fmt_sdr_cap,
1025 .vidioc_s_fmt_sdr_cap = rcar_drif_s_fmt_sdr_cap,
1026 .vidioc_try_fmt_sdr_cap = rcar_drif_try_fmt_sdr_cap,
1027
1028 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1029 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1030 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1031 .vidioc_querybuf = vb2_ioctl_querybuf,
1032 .vidioc_qbuf = vb2_ioctl_qbuf,
1033 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1034
1035 .vidioc_streamon = vb2_ioctl_streamon,
1036 .vidioc_streamoff = vb2_ioctl_streamoff,
1037
1038 .vidioc_s_frequency = rcar_drif_s_frequency,
1039 .vidioc_g_frequency = rcar_drif_g_frequency,
1040 .vidioc_s_tuner = rcar_drif_s_tuner,
1041 .vidioc_g_tuner = rcar_drif_g_tuner,
1042 .vidioc_enum_freq_bands = rcar_drif_enum_freq_bands,
1043 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1044 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1045 .vidioc_log_status = v4l2_ctrl_log_status,
1046 };
1047
1048 static const struct v4l2_file_operations rcar_drif_fops = {
1049 .owner = THIS_MODULE,
1050 .open = v4l2_fh_open,
1051 .release = vb2_fop_release,
1052 .read = vb2_fop_read,
1053 .poll = vb2_fop_poll,
1054 .mmap = vb2_fop_mmap,
1055 .unlocked_ioctl = video_ioctl2,
1056 };
1057
rcar_drif_sdr_register(struct rcar_drif_sdr * sdr)1058 static int rcar_drif_sdr_register(struct rcar_drif_sdr *sdr)
1059 {
1060 int ret;
1061
1062 /* Init video_device structure */
1063 sdr->vdev = video_device_alloc();
1064 if (!sdr->vdev)
1065 return -ENOMEM;
1066
1067 snprintf(sdr->vdev->name, sizeof(sdr->vdev->name), "R-Car DRIF");
1068 sdr->vdev->fops = &rcar_drif_fops;
1069 sdr->vdev->ioctl_ops = &rcar_drif_ioctl_ops;
1070 sdr->vdev->release = video_device_release;
1071 sdr->vdev->lock = &sdr->v4l2_mutex;
1072 sdr->vdev->queue = &sdr->vb_queue;
1073 sdr->vdev->queue->lock = &sdr->vb_queue_mutex;
1074 sdr->vdev->ctrl_handler = &sdr->ctrl_hdl;
1075 sdr->vdev->v4l2_dev = &sdr->v4l2_dev;
1076 sdr->vdev->device_caps = V4L2_CAP_SDR_CAPTURE | V4L2_CAP_TUNER |
1077 V4L2_CAP_STREAMING | V4L2_CAP_READWRITE;
1078 video_set_drvdata(sdr->vdev, sdr);
1079
1080 /* Register V4L2 SDR device */
1081 ret = video_register_device(sdr->vdev, VFL_TYPE_SDR, -1);
1082 if (ret) {
1083 video_device_release(sdr->vdev);
1084 sdr->vdev = NULL;
1085 dev_err(sdr->dev, "failed video_register_device (%d)\n", ret);
1086 }
1087
1088 return ret;
1089 }
1090
rcar_drif_sdr_unregister(struct rcar_drif_sdr * sdr)1091 static void rcar_drif_sdr_unregister(struct rcar_drif_sdr *sdr)
1092 {
1093 video_unregister_device(sdr->vdev);
1094 sdr->vdev = NULL;
1095 }
1096
1097 /* Sub-device bound callback */
rcar_drif_notify_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)1098 static int rcar_drif_notify_bound(struct v4l2_async_notifier *notifier,
1099 struct v4l2_subdev *subdev,
1100 struct v4l2_async_subdev *asd)
1101 {
1102 struct rcar_drif_sdr *sdr =
1103 container_of(notifier, struct rcar_drif_sdr, notifier);
1104
1105 v4l2_set_subdev_hostdata(subdev, sdr);
1106 sdr->ep.subdev = subdev;
1107 rdrif_dbg(sdr, "bound asd %s\n", subdev->name);
1108
1109 return 0;
1110 }
1111
1112 /* Sub-device unbind callback */
rcar_drif_notify_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)1113 static void rcar_drif_notify_unbind(struct v4l2_async_notifier *notifier,
1114 struct v4l2_subdev *subdev,
1115 struct v4l2_async_subdev *asd)
1116 {
1117 struct rcar_drif_sdr *sdr =
1118 container_of(notifier, struct rcar_drif_sdr, notifier);
1119
1120 if (sdr->ep.subdev != subdev) {
1121 rdrif_err(sdr, "subdev %s is not bound\n", subdev->name);
1122 return;
1123 }
1124
1125 /* Free ctrl handler if initialized */
1126 v4l2_ctrl_handler_free(&sdr->ctrl_hdl);
1127 sdr->v4l2_dev.ctrl_handler = NULL;
1128 sdr->ep.subdev = NULL;
1129
1130 rcar_drif_sdr_unregister(sdr);
1131 rdrif_dbg(sdr, "unbind asd %s\n", subdev->name);
1132 }
1133
1134 /* Sub-device registered notification callback */
rcar_drif_notify_complete(struct v4l2_async_notifier * notifier)1135 static int rcar_drif_notify_complete(struct v4l2_async_notifier *notifier)
1136 {
1137 struct rcar_drif_sdr *sdr =
1138 container_of(notifier, struct rcar_drif_sdr, notifier);
1139 int ret;
1140
1141 /*
1142 * The subdev tested at this point uses 4 controls. Using 10 as a worst
1143 * case scenario hint. When less controls are needed there will be some
1144 * unused memory and when more controls are needed the framework uses
1145 * hash to manage controls within this number.
1146 */
1147 ret = v4l2_ctrl_handler_init(&sdr->ctrl_hdl, 10);
1148 if (ret)
1149 return -ENOMEM;
1150
1151 sdr->v4l2_dev.ctrl_handler = &sdr->ctrl_hdl;
1152 ret = v4l2_device_register_subdev_nodes(&sdr->v4l2_dev);
1153 if (ret) {
1154 rdrif_err(sdr, "failed: register subdev nodes ret %d\n", ret);
1155 goto error;
1156 }
1157
1158 ret = v4l2_ctrl_add_handler(&sdr->ctrl_hdl,
1159 sdr->ep.subdev->ctrl_handler, NULL, true);
1160 if (ret) {
1161 rdrif_err(sdr, "failed: ctrl add hdlr ret %d\n", ret);
1162 goto error;
1163 }
1164
1165 ret = rcar_drif_sdr_register(sdr);
1166 if (ret)
1167 goto error;
1168
1169 return ret;
1170
1171 error:
1172 v4l2_ctrl_handler_free(&sdr->ctrl_hdl);
1173
1174 return ret;
1175 }
1176
1177 static const struct v4l2_async_notifier_operations rcar_drif_notify_ops = {
1178 .bound = rcar_drif_notify_bound,
1179 .unbind = rcar_drif_notify_unbind,
1180 .complete = rcar_drif_notify_complete,
1181 };
1182
1183 /* Read endpoint properties */
rcar_drif_get_ep_properties(struct rcar_drif_sdr * sdr,struct fwnode_handle * fwnode)1184 static void rcar_drif_get_ep_properties(struct rcar_drif_sdr *sdr,
1185 struct fwnode_handle *fwnode)
1186 {
1187 u32 val;
1188
1189 /* Set the I2S defaults for SIRMDR1*/
1190 sdr->mdr1 = RCAR_DRIF_SIRMDR1_SYNCMD_LR | RCAR_DRIF_SIRMDR1_MSB_FIRST |
1191 RCAR_DRIF_SIRMDR1_DTDL_1 | RCAR_DRIF_SIRMDR1_SYNCDL_0;
1192
1193 /* Parse sync polarity from endpoint */
1194 if (!fwnode_property_read_u32(fwnode, "sync-active", &val))
1195 sdr->mdr1 |= val ? RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH :
1196 RCAR_DRIF_SIRMDR1_SYNCAC_POL_LOW;
1197 else
1198 sdr->mdr1 |= RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH; /* default */
1199
1200 dev_dbg(sdr->dev, "mdr1 0x%08x\n", sdr->mdr1);
1201 }
1202
1203 /* Parse sub-devs (tuner) to find a matching device */
rcar_drif_parse_subdevs(struct rcar_drif_sdr * sdr)1204 static int rcar_drif_parse_subdevs(struct rcar_drif_sdr *sdr)
1205 {
1206 struct v4l2_async_notifier *notifier = &sdr->notifier;
1207 struct fwnode_handle *fwnode, *ep;
1208 struct v4l2_async_subdev *asd;
1209
1210 v4l2_async_nf_init(notifier);
1211
1212 ep = fwnode_graph_get_next_endpoint(of_fwnode_handle(sdr->dev->of_node),
1213 NULL);
1214 if (!ep)
1215 return 0;
1216
1217 /* Get the endpoint properties */
1218 rcar_drif_get_ep_properties(sdr, ep);
1219
1220 fwnode = fwnode_graph_get_remote_port_parent(ep);
1221 fwnode_handle_put(ep);
1222 if (!fwnode) {
1223 dev_warn(sdr->dev, "bad remote port parent\n");
1224 return -EINVAL;
1225 }
1226
1227 asd = v4l2_async_nf_add_fwnode(notifier, fwnode,
1228 struct v4l2_async_subdev);
1229 fwnode_handle_put(fwnode);
1230 if (IS_ERR(asd))
1231 return PTR_ERR(asd);
1232
1233 return 0;
1234 }
1235
1236 /* Check if the given device is the primary bond */
rcar_drif_primary_bond(struct platform_device * pdev)1237 static bool rcar_drif_primary_bond(struct platform_device *pdev)
1238 {
1239 return of_property_read_bool(pdev->dev.of_node, "renesas,primary-bond");
1240 }
1241
1242 /* Check if both devices of the bond are enabled */
rcar_drif_bond_enabled(struct platform_device * p)1243 static struct device_node *rcar_drif_bond_enabled(struct platform_device *p)
1244 {
1245 struct device_node *np;
1246
1247 np = of_parse_phandle(p->dev.of_node, "renesas,bonding", 0);
1248 if (np && of_device_is_available(np))
1249 return np;
1250
1251 return NULL;
1252 }
1253
1254 /* Check if the bonded device is probed */
rcar_drif_bond_available(struct rcar_drif_sdr * sdr,struct device_node * np)1255 static int rcar_drif_bond_available(struct rcar_drif_sdr *sdr,
1256 struct device_node *np)
1257 {
1258 struct platform_device *pdev;
1259 struct rcar_drif *ch;
1260 int ret = 0;
1261
1262 pdev = of_find_device_by_node(np);
1263 if (!pdev) {
1264 dev_err(sdr->dev, "failed to get bonded device from node\n");
1265 return -ENODEV;
1266 }
1267
1268 device_lock(&pdev->dev);
1269 ch = platform_get_drvdata(pdev);
1270 if (ch) {
1271 /* Update sdr data in the bonded device */
1272 ch->sdr = sdr;
1273
1274 /* Update sdr with bonded device data */
1275 sdr->ch[ch->num] = ch;
1276 sdr->hw_ch_mask |= BIT(ch->num);
1277 } else {
1278 /* Defer */
1279 dev_info(sdr->dev, "defer probe\n");
1280 ret = -EPROBE_DEFER;
1281 }
1282 device_unlock(&pdev->dev);
1283
1284 put_device(&pdev->dev);
1285
1286 return ret;
1287 }
1288
1289 /* V4L2 SDR device probe */
rcar_drif_sdr_probe(struct rcar_drif_sdr * sdr)1290 static int rcar_drif_sdr_probe(struct rcar_drif_sdr *sdr)
1291 {
1292 int ret;
1293
1294 /* Validate any supported format for enabled channels */
1295 ret = rcar_drif_set_default_format(sdr);
1296 if (ret) {
1297 dev_err(sdr->dev, "failed to set default format\n");
1298 return ret;
1299 }
1300
1301 /* Set defaults */
1302 sdr->hwbuf_size = RCAR_DRIF_DEFAULT_HWBUF_SIZE;
1303
1304 mutex_init(&sdr->v4l2_mutex);
1305 mutex_init(&sdr->vb_queue_mutex);
1306 spin_lock_init(&sdr->queued_bufs_lock);
1307 spin_lock_init(&sdr->dma_lock);
1308 INIT_LIST_HEAD(&sdr->queued_bufs);
1309
1310 /* Init videobuf2 queue structure */
1311 sdr->vb_queue.type = V4L2_BUF_TYPE_SDR_CAPTURE;
1312 sdr->vb_queue.io_modes = VB2_READ | VB2_MMAP | VB2_DMABUF;
1313 sdr->vb_queue.drv_priv = sdr;
1314 sdr->vb_queue.buf_struct_size = sizeof(struct rcar_drif_frame_buf);
1315 sdr->vb_queue.ops = &rcar_drif_vb2_ops;
1316 sdr->vb_queue.mem_ops = &vb2_vmalloc_memops;
1317 sdr->vb_queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1318
1319 /* Init videobuf2 queue */
1320 ret = vb2_queue_init(&sdr->vb_queue);
1321 if (ret) {
1322 dev_err(sdr->dev, "failed: vb2_queue_init ret %d\n", ret);
1323 return ret;
1324 }
1325
1326 /* Register the v4l2_device */
1327 ret = v4l2_device_register(sdr->dev, &sdr->v4l2_dev);
1328 if (ret) {
1329 dev_err(sdr->dev, "failed: v4l2_device_register ret %d\n", ret);
1330 return ret;
1331 }
1332
1333 /*
1334 * Parse subdevs after v4l2_device_register because if the subdev
1335 * is already probed, bound and complete will be called immediately
1336 */
1337 ret = rcar_drif_parse_subdevs(sdr);
1338 if (ret)
1339 goto error;
1340
1341 sdr->notifier.ops = &rcar_drif_notify_ops;
1342
1343 /* Register notifier */
1344 ret = v4l2_async_nf_register(&sdr->v4l2_dev, &sdr->notifier);
1345 if (ret < 0) {
1346 dev_err(sdr->dev, "failed: notifier register ret %d\n", ret);
1347 goto cleanup;
1348 }
1349
1350 return ret;
1351
1352 cleanup:
1353 v4l2_async_nf_cleanup(&sdr->notifier);
1354 error:
1355 v4l2_device_unregister(&sdr->v4l2_dev);
1356
1357 return ret;
1358 }
1359
1360 /* V4L2 SDR device remove */
rcar_drif_sdr_remove(struct rcar_drif_sdr * sdr)1361 static void rcar_drif_sdr_remove(struct rcar_drif_sdr *sdr)
1362 {
1363 v4l2_async_nf_unregister(&sdr->notifier);
1364 v4l2_async_nf_cleanup(&sdr->notifier);
1365 v4l2_device_unregister(&sdr->v4l2_dev);
1366 }
1367
1368 /* DRIF channel probe */
rcar_drif_probe(struct platform_device * pdev)1369 static int rcar_drif_probe(struct platform_device *pdev)
1370 {
1371 struct rcar_drif_sdr *sdr;
1372 struct device_node *np;
1373 struct rcar_drif *ch;
1374 struct resource *res;
1375 int ret;
1376
1377 /* Reserve memory for enabled channel */
1378 ch = devm_kzalloc(&pdev->dev, sizeof(*ch), GFP_KERNEL);
1379 if (!ch)
1380 return -ENOMEM;
1381
1382 ch->pdev = pdev;
1383
1384 /* Module clock */
1385 ch->clk = devm_clk_get(&pdev->dev, "fck");
1386 if (IS_ERR(ch->clk)) {
1387 ret = PTR_ERR(ch->clk);
1388 dev_err(&pdev->dev, "clk get failed (%d)\n", ret);
1389 return ret;
1390 }
1391
1392 /* Register map */
1393 ch->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1394 if (IS_ERR(ch->base))
1395 return PTR_ERR(ch->base);
1396
1397 ch->start = res->start;
1398 platform_set_drvdata(pdev, ch);
1399
1400 /* Check if both channels of the bond are enabled */
1401 np = rcar_drif_bond_enabled(pdev);
1402 if (np) {
1403 /* Check if current channel acting as primary-bond */
1404 if (!rcar_drif_primary_bond(pdev)) {
1405 ch->num = 1; /* Primary bond is channel 0 always */
1406 of_node_put(np);
1407 return 0;
1408 }
1409 }
1410
1411 /* Reserve memory for SDR structure */
1412 sdr = devm_kzalloc(&pdev->dev, sizeof(*sdr), GFP_KERNEL);
1413 if (!sdr) {
1414 of_node_put(np);
1415 return -ENOMEM;
1416 }
1417 ch->sdr = sdr;
1418 sdr->dev = &pdev->dev;
1419
1420 /* Establish links between SDR and channel(s) */
1421 sdr->ch[ch->num] = ch;
1422 sdr->hw_ch_mask = BIT(ch->num);
1423 if (np) {
1424 /* Check if bonded device is ready */
1425 ret = rcar_drif_bond_available(sdr, np);
1426 of_node_put(np);
1427 if (ret)
1428 return ret;
1429 }
1430 sdr->num_hw_ch = hweight_long(sdr->hw_ch_mask);
1431
1432 return rcar_drif_sdr_probe(sdr);
1433 }
1434
1435 /* DRIF channel remove */
rcar_drif_remove(struct platform_device * pdev)1436 static int rcar_drif_remove(struct platform_device *pdev)
1437 {
1438 struct rcar_drif *ch = platform_get_drvdata(pdev);
1439 struct rcar_drif_sdr *sdr = ch->sdr;
1440
1441 /* Channel 0 will be the SDR instance */
1442 if (ch->num)
1443 return 0;
1444
1445 /* SDR instance */
1446 rcar_drif_sdr_remove(sdr);
1447
1448 return 0;
1449 }
1450
1451 /* FIXME: Implement suspend/resume support */
rcar_drif_suspend(struct device * dev)1452 static int __maybe_unused rcar_drif_suspend(struct device *dev)
1453 {
1454 return 0;
1455 }
1456
rcar_drif_resume(struct device * dev)1457 static int __maybe_unused rcar_drif_resume(struct device *dev)
1458 {
1459 return 0;
1460 }
1461
1462 static SIMPLE_DEV_PM_OPS(rcar_drif_pm_ops, rcar_drif_suspend,
1463 rcar_drif_resume);
1464
1465 static const struct of_device_id rcar_drif_of_table[] = {
1466 { .compatible = "renesas,rcar-gen3-drif" },
1467 { }
1468 };
1469 MODULE_DEVICE_TABLE(of, rcar_drif_of_table);
1470
1471 #define RCAR_DRIF_DRV_NAME "rcar_drif"
1472 static struct platform_driver rcar_drif_driver = {
1473 .driver = {
1474 .name = RCAR_DRIF_DRV_NAME,
1475 .of_match_table = rcar_drif_of_table,
1476 .pm = &rcar_drif_pm_ops,
1477 },
1478 .probe = rcar_drif_probe,
1479 .remove = rcar_drif_remove,
1480 };
1481
1482 module_platform_driver(rcar_drif_driver);
1483
1484 MODULE_DESCRIPTION("Renesas R-Car Gen3 DRIF driver");
1485 MODULE_ALIAS("platform:" RCAR_DRIF_DRV_NAME);
1486 MODULE_LICENSE("GPL");
1487 MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
1488