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1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Microchip switch driver common header
3  *
4  * Copyright (C) 2017-2019 Microchip Technology Inc.
5  */
6 
7 #ifndef __KSZ_COMMON_H
8 #define __KSZ_COMMON_H
9 
10 #include <linux/etherdevice.h>
11 #include <linux/kernel.h>
12 #include <linux/mutex.h>
13 #include <linux/phy.h>
14 #include <linux/regmap.h>
15 #include <net/dsa.h>
16 #include <linux/irq.h>
17 
18 #define KSZ_MAX_NUM_PORTS 8
19 
20 struct ksz_device;
21 
22 struct vlan_table {
23 	u32 table[3];
24 };
25 
26 struct ksz_port_mib {
27 	struct mutex cnt_mutex;		/* structure access */
28 	u8 cnt_ptr;
29 	u64 *counters;
30 	struct rtnl_link_stats64 stats64;
31 	struct ethtool_pause_stats pause_stats;
32 	struct spinlock stats64_lock;
33 };
34 
35 struct ksz_mib_names {
36 	int index;
37 	char string[ETH_GSTRING_LEN];
38 };
39 
40 struct ksz_chip_data {
41 	u32 chip_id;
42 	const char *dev_name;
43 	int num_vlans;
44 	int num_alus;
45 	int num_statics;
46 	int cpu_ports;
47 	int port_cnt;
48 	u8 port_nirqs;
49 	const struct ksz_dev_ops *ops;
50 	bool phy_errata_9477;
51 	bool ksz87xx_eee_link_erratum;
52 	const struct ksz_mib_names *mib_names;
53 	int mib_cnt;
54 	u8 reg_mib_cnt;
55 	const u16 *regs;
56 	const u32 *masks;
57 	const u8 *shifts;
58 	const u8 *xmii_ctrl0;
59 	const u8 *xmii_ctrl1;
60 	int stp_ctrl_reg;
61 	int broadcast_ctrl_reg;
62 	int multicast_ctrl_reg;
63 	int start_ctrl_reg;
64 	bool supports_mii[KSZ_MAX_NUM_PORTS];
65 	bool supports_rmii[KSZ_MAX_NUM_PORTS];
66 	bool supports_rgmii[KSZ_MAX_NUM_PORTS];
67 	bool internal_phy[KSZ_MAX_NUM_PORTS];
68 	bool gbit_capable[KSZ_MAX_NUM_PORTS];
69 	const struct regmap_access_table *wr_table;
70 	const struct regmap_access_table *rd_table;
71 };
72 
73 struct ksz_irq {
74 	u16 masked;
75 	u16 reg_mask;
76 	u16 reg_status;
77 	struct irq_domain *domain;
78 	int nirqs;
79 	int irq_num;
80 	char name[16];
81 	struct ksz_device *dev;
82 };
83 
84 struct ksz_port {
85 	bool remove_tag;		/* Remove Tag flag set, for ksz8795 only */
86 	bool learning;
87 	int stp_state;
88 	struct phy_device phydev;
89 
90 	u32 on:1;			/* port is not disabled by hardware */
91 	u32 fiber:1;			/* port is fiber */
92 	u32 force:1;
93 	u32 read:1;			/* read MIB counters in background */
94 	u32 freeze:1;			/* MIB counter freeze is enabled */
95 
96 	struct ksz_port_mib mib;
97 	phy_interface_t interface;
98 	u16 max_frame;
99 	u32 rgmii_tx_val;
100 	u32 rgmii_rx_val;
101 	struct ksz_device *ksz_dev;
102 	struct ksz_irq pirq;
103 	u8 num;
104 };
105 
106 struct ksz_device {
107 	struct dsa_switch *ds;
108 	struct ksz_platform_data *pdata;
109 	const struct ksz_chip_data *info;
110 
111 	struct mutex dev_mutex;		/* device access */
112 	struct mutex regmap_mutex;	/* regmap access */
113 	struct mutex alu_mutex;		/* ALU access */
114 	struct mutex vlan_mutex;	/* vlan access */
115 	const struct ksz_dev_ops *dev_ops;
116 
117 	struct device *dev;
118 	struct regmap *regmap[3];
119 
120 	void *priv;
121 	int irq;
122 
123 	struct gpio_desc *reset_gpio;	/* Optional reset GPIO */
124 
125 	/* chip specific data */
126 	u32 chip_id;
127 	u8 chip_rev;
128 	int cpu_port;			/* port connected to CPU */
129 	int phy_port_cnt;
130 	phy_interface_t compat_interface;
131 	bool synclko_125;
132 	bool synclko_disable;
133 
134 	struct vlan_table *vlan_cache;
135 
136 	struct ksz_port *ports;
137 	struct delayed_work mib_read;
138 	unsigned long mib_read_interval;
139 	u16 mirror_rx;
140 	u16 mirror_tx;
141 	u16 port_mask;
142 	struct mutex lock_irq;		/* IRQ Access */
143 	struct ksz_irq girq;
144 };
145 
146 /* List of supported models */
147 enum ksz_model {
148 	KSZ8563,
149 	KSZ8795,
150 	KSZ8794,
151 	KSZ8765,
152 	KSZ8830,
153 	KSZ9477,
154 	KSZ9896,
155 	KSZ9897,
156 	KSZ9893,
157 	KSZ9567,
158 	LAN9370,
159 	LAN9371,
160 	LAN9372,
161 	LAN9373,
162 	LAN9374,
163 };
164 
165 enum ksz_chip_id {
166 	KSZ8563_CHIP_ID = 0x8563,
167 	KSZ8795_CHIP_ID = 0x8795,
168 	KSZ8794_CHIP_ID = 0x8794,
169 	KSZ8765_CHIP_ID = 0x8765,
170 	KSZ8830_CHIP_ID = 0x8830,
171 	KSZ9477_CHIP_ID = 0x00947700,
172 	KSZ9896_CHIP_ID = 0x00989600,
173 	KSZ9897_CHIP_ID = 0x00989700,
174 	KSZ9893_CHIP_ID = 0x00989300,
175 	KSZ9567_CHIP_ID = 0x00956700,
176 	LAN9370_CHIP_ID = 0x00937000,
177 	LAN9371_CHIP_ID = 0x00937100,
178 	LAN9372_CHIP_ID = 0x00937200,
179 	LAN9373_CHIP_ID = 0x00937300,
180 	LAN9374_CHIP_ID = 0x00937400,
181 };
182 
183 enum ksz_regs {
184 	REG_IND_CTRL_0,
185 	REG_IND_DATA_8,
186 	REG_IND_DATA_CHECK,
187 	REG_IND_DATA_HI,
188 	REG_IND_DATA_LO,
189 	REG_IND_MIB_CHECK,
190 	REG_IND_BYTE,
191 	P_FORCE_CTRL,
192 	P_LINK_STATUS,
193 	P_LOCAL_CTRL,
194 	P_NEG_RESTART_CTRL,
195 	P_REMOTE_STATUS,
196 	P_SPEED_STATUS,
197 	S_TAIL_TAG_CTRL,
198 	P_STP_CTRL,
199 	S_START_CTRL,
200 	S_BROADCAST_CTRL,
201 	S_MULTICAST_CTRL,
202 	P_XMII_CTRL_0,
203 	P_XMII_CTRL_1,
204 };
205 
206 enum ksz_masks {
207 	PORT_802_1P_REMAPPING,
208 	SW_TAIL_TAG_ENABLE,
209 	MIB_COUNTER_OVERFLOW,
210 	MIB_COUNTER_VALID,
211 	VLAN_TABLE_FID,
212 	VLAN_TABLE_MEMBERSHIP,
213 	VLAN_TABLE_VALID,
214 	STATIC_MAC_TABLE_VALID,
215 	STATIC_MAC_TABLE_USE_FID,
216 	STATIC_MAC_TABLE_FID,
217 	STATIC_MAC_TABLE_OVERRIDE,
218 	STATIC_MAC_TABLE_FWD_PORTS,
219 	DYNAMIC_MAC_TABLE_ENTRIES_H,
220 	DYNAMIC_MAC_TABLE_MAC_EMPTY,
221 	DYNAMIC_MAC_TABLE_NOT_READY,
222 	DYNAMIC_MAC_TABLE_ENTRIES,
223 	DYNAMIC_MAC_TABLE_FID,
224 	DYNAMIC_MAC_TABLE_SRC_PORT,
225 	DYNAMIC_MAC_TABLE_TIMESTAMP,
226 	ALU_STAT_WRITE,
227 	ALU_STAT_READ,
228 	P_MII_TX_FLOW_CTRL,
229 	P_MII_RX_FLOW_CTRL,
230 };
231 
232 enum ksz_shifts {
233 	VLAN_TABLE_MEMBERSHIP_S,
234 	VLAN_TABLE,
235 	STATIC_MAC_FWD_PORTS,
236 	STATIC_MAC_FID,
237 	DYNAMIC_MAC_ENTRIES_H,
238 	DYNAMIC_MAC_ENTRIES,
239 	DYNAMIC_MAC_FID,
240 	DYNAMIC_MAC_TIMESTAMP,
241 	DYNAMIC_MAC_SRC_PORT,
242 	ALU_STAT_INDEX,
243 };
244 
245 enum ksz_xmii_ctrl0 {
246 	P_MII_100MBIT,
247 	P_MII_10MBIT,
248 	P_MII_FULL_DUPLEX,
249 	P_MII_HALF_DUPLEX,
250 };
251 
252 enum ksz_xmii_ctrl1 {
253 	P_RGMII_SEL,
254 	P_RMII_SEL,
255 	P_GMII_SEL,
256 	P_MII_SEL,
257 	P_GMII_1GBIT,
258 	P_GMII_NOT_1GBIT,
259 };
260 
261 struct alu_struct {
262 	/* entry 1 */
263 	u8	is_static:1;
264 	u8	is_src_filter:1;
265 	u8	is_dst_filter:1;
266 	u8	prio_age:3;
267 	u32	_reserv_0_1:23;
268 	u8	mstp:3;
269 	/* entry 2 */
270 	u8	is_override:1;
271 	u8	is_use_fid:1;
272 	u32	_reserv_1_1:23;
273 	u8	port_forward:7;
274 	/* entry 3 & 4*/
275 	u32	_reserv_2_1:9;
276 	u8	fid:7;
277 	u8	mac[ETH_ALEN];
278 };
279 
280 struct ksz_dev_ops {
281 	int (*setup)(struct dsa_switch *ds);
282 	void (*teardown)(struct dsa_switch *ds);
283 	u32 (*get_port_addr)(int port, int offset);
284 	void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member);
285 	void (*flush_dyn_mac_table)(struct ksz_device *dev, int port);
286 	void (*port_cleanup)(struct ksz_device *dev, int port);
287 	void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port);
288 	int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs);
289 	int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val);
290 	int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val);
291 	void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr,
292 			  u64 *cnt);
293 	void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr,
294 			  u64 *dropped, u64 *cnt);
295 	void (*r_mib_stat64)(struct ksz_device *dev, int port);
296 	int  (*vlan_filtering)(struct ksz_device *dev, int port,
297 			       bool flag, struct netlink_ext_ack *extack);
298 	int  (*vlan_add)(struct ksz_device *dev, int port,
299 			 const struct switchdev_obj_port_vlan *vlan,
300 			 struct netlink_ext_ack *extack);
301 	int  (*vlan_del)(struct ksz_device *dev, int port,
302 			 const struct switchdev_obj_port_vlan *vlan);
303 	int (*mirror_add)(struct ksz_device *dev, int port,
304 			  struct dsa_mall_mirror_tc_entry *mirror,
305 			  bool ingress, struct netlink_ext_ack *extack);
306 	void (*mirror_del)(struct ksz_device *dev, int port,
307 			   struct dsa_mall_mirror_tc_entry *mirror);
308 	int (*fdb_add)(struct ksz_device *dev, int port,
309 		       const unsigned char *addr, u16 vid, struct dsa_db db);
310 	int (*fdb_del)(struct ksz_device *dev, int port,
311 		       const unsigned char *addr, u16 vid, struct dsa_db db);
312 	int (*fdb_dump)(struct ksz_device *dev, int port,
313 			dsa_fdb_dump_cb_t *cb, void *data);
314 	int (*mdb_add)(struct ksz_device *dev, int port,
315 		       const struct switchdev_obj_port_mdb *mdb,
316 		       struct dsa_db db);
317 	int (*mdb_del)(struct ksz_device *dev, int port,
318 		       const struct switchdev_obj_port_mdb *mdb,
319 		       struct dsa_db db);
320 	void (*get_caps)(struct ksz_device *dev, int port,
321 			 struct phylink_config *config);
322 	int (*change_mtu)(struct ksz_device *dev, int port, int mtu);
323 	int (*max_mtu)(struct ksz_device *dev, int port);
324 	void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze);
325 	void (*port_init_cnt)(struct ksz_device *dev, int port);
326 	void (*phylink_mac_config)(struct ksz_device *dev, int port,
327 				   unsigned int mode,
328 				   const struct phylink_link_state *state);
329 	void (*phylink_mac_link_up)(struct ksz_device *dev, int port,
330 				    unsigned int mode,
331 				    phy_interface_t interface,
332 				    struct phy_device *phydev, int speed,
333 				    int duplex, bool tx_pause, bool rx_pause);
334 	void (*setup_rgmii_delay)(struct ksz_device *dev, int port);
335 	void (*config_cpu_port)(struct dsa_switch *ds);
336 	int (*enable_stp_addr)(struct ksz_device *dev);
337 	int (*reset)(struct ksz_device *dev);
338 	int (*init)(struct ksz_device *dev);
339 	void (*exit)(struct ksz_device *dev);
340 };
341 
342 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv);
343 int ksz_switch_register(struct ksz_device *dev);
344 void ksz_switch_remove(struct ksz_device *dev);
345 
346 void ksz_init_mib_timer(struct ksz_device *dev);
347 void ksz_r_mib_stats64(struct ksz_device *dev, int port);
348 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
349 bool ksz_get_gbit(struct ksz_device *dev, int port);
350 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit);
351 extern const struct ksz_chip_data ksz_switch_chips[];
352 
353 /* Common register access functions */
354 
ksz_read8(struct ksz_device * dev,u32 reg,u8 * val)355 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val)
356 {
357 	unsigned int value;
358 	int ret = regmap_read(dev->regmap[0], reg, &value);
359 
360 	if (ret)
361 		dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg,
362 			ERR_PTR(ret));
363 
364 	*val = value;
365 	return ret;
366 }
367 
ksz_read16(struct ksz_device * dev,u32 reg,u16 * val)368 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val)
369 {
370 	unsigned int value;
371 	int ret = regmap_read(dev->regmap[1], reg, &value);
372 
373 	if (ret)
374 		dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg,
375 			ERR_PTR(ret));
376 
377 	*val = value;
378 	return ret;
379 }
380 
ksz_read32(struct ksz_device * dev,u32 reg,u32 * val)381 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val)
382 {
383 	unsigned int value;
384 	int ret = regmap_read(dev->regmap[2], reg, &value);
385 
386 	if (ret)
387 		dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg,
388 			ERR_PTR(ret));
389 
390 	*val = value;
391 	return ret;
392 }
393 
ksz_read64(struct ksz_device * dev,u32 reg,u64 * val)394 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val)
395 {
396 	u32 value[2];
397 	int ret;
398 
399 	ret = regmap_bulk_read(dev->regmap[2], reg, value, 2);
400 	if (ret)
401 		dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg,
402 			ERR_PTR(ret));
403 	else
404 		*val = (u64)value[0] << 32 | value[1];
405 
406 	return ret;
407 }
408 
ksz_write8(struct ksz_device * dev,u32 reg,u8 value)409 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value)
410 {
411 	int ret;
412 
413 	ret = regmap_write(dev->regmap[0], reg, value);
414 	if (ret)
415 		dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg,
416 			ERR_PTR(ret));
417 
418 	return ret;
419 }
420 
ksz_write16(struct ksz_device * dev,u32 reg,u16 value)421 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value)
422 {
423 	int ret;
424 
425 	ret = regmap_write(dev->regmap[1], reg, value);
426 	if (ret)
427 		dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg,
428 			ERR_PTR(ret));
429 
430 	return ret;
431 }
432 
ksz_write32(struct ksz_device * dev,u32 reg,u32 value)433 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value)
434 {
435 	int ret;
436 
437 	ret = regmap_write(dev->regmap[2], reg, value);
438 	if (ret)
439 		dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg,
440 			ERR_PTR(ret));
441 
442 	return ret;
443 }
444 
ksz_write64(struct ksz_device * dev,u32 reg,u64 value)445 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value)
446 {
447 	u32 val[2];
448 
449 	/* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */
450 	value = swab64(value);
451 	val[0] = swab32(value & 0xffffffffULL);
452 	val[1] = swab32(value >> 32ULL);
453 
454 	return regmap_bulk_write(dev->regmap[2], reg, val, 2);
455 }
456 
ksz_pread8(struct ksz_device * dev,int port,int offset,u8 * data)457 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset,
458 			     u8 *data)
459 {
460 	return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data);
461 }
462 
ksz_pread16(struct ksz_device * dev,int port,int offset,u16 * data)463 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset,
464 			      u16 *data)
465 {
466 	return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data);
467 }
468 
ksz_pread32(struct ksz_device * dev,int port,int offset,u32 * data)469 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset,
470 			      u32 *data)
471 {
472 	return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data);
473 }
474 
ksz_pwrite8(struct ksz_device * dev,int port,int offset,u8 data)475 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset,
476 			      u8 data)
477 {
478 	return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data);
479 }
480 
ksz_pwrite16(struct ksz_device * dev,int port,int offset,u16 data)481 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset,
482 			       u16 data)
483 {
484 	return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset),
485 			   data);
486 }
487 
ksz_pwrite32(struct ksz_device * dev,int port,int offset,u32 data)488 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset,
489 			       u32 data)
490 {
491 	return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset),
492 			   data);
493 }
494 
ksz_prmw8(struct ksz_device * dev,int port,int offset,u8 mask,u8 val)495 static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset,
496 			     u8 mask, u8 val)
497 {
498 	regmap_update_bits(dev->regmap[0],
499 			   dev->dev_ops->get_port_addr(port, offset),
500 			   mask, val);
501 }
502 
ksz_regmap_lock(void * __mtx)503 static inline void ksz_regmap_lock(void *__mtx)
504 {
505 	struct mutex *mtx = __mtx;
506 	mutex_lock(mtx);
507 }
508 
ksz_regmap_unlock(void * __mtx)509 static inline void ksz_regmap_unlock(void *__mtx)
510 {
511 	struct mutex *mtx = __mtx;
512 	mutex_unlock(mtx);
513 }
514 
ksz_is_ksz87xx(struct ksz_device * dev)515 static inline bool ksz_is_ksz87xx(struct ksz_device *dev)
516 {
517 	return dev->chip_id == KSZ8795_CHIP_ID ||
518 	       dev->chip_id == KSZ8794_CHIP_ID ||
519 	       dev->chip_id == KSZ8765_CHIP_ID;
520 }
521 
ksz_is_ksz88x3(struct ksz_device * dev)522 static inline bool ksz_is_ksz88x3(struct ksz_device *dev)
523 {
524 	return dev->chip_id == KSZ8830_CHIP_ID;
525 }
526 
is_lan937x(struct ksz_device * dev)527 static inline int is_lan937x(struct ksz_device *dev)
528 {
529 	return dev->chip_id == LAN9370_CHIP_ID ||
530 		dev->chip_id == LAN9371_CHIP_ID ||
531 		dev->chip_id == LAN9372_CHIP_ID ||
532 		dev->chip_id == LAN9373_CHIP_ID ||
533 		dev->chip_id == LAN9374_CHIP_ID;
534 }
535 
536 /* STP State Defines */
537 #define PORT_TX_ENABLE			BIT(2)
538 #define PORT_RX_ENABLE			BIT(1)
539 #define PORT_LEARN_DISABLE		BIT(0)
540 
541 /* Switch ID Defines */
542 #define REG_CHIP_ID0			0x00
543 
544 #define SW_FAMILY_ID_M			GENMASK(15, 8)
545 #define KSZ87_FAMILY_ID			0x87
546 #define KSZ88_FAMILY_ID			0x88
547 
548 #define KSZ8_PORT_STATUS_0		0x08
549 #define KSZ8_PORT_FIBER_MODE		BIT(7)
550 
551 #define SW_CHIP_ID_M			GENMASK(7, 4)
552 #define KSZ87_CHIP_ID_94		0x6
553 #define KSZ87_CHIP_ID_95		0x9
554 #define KSZ88_CHIP_ID_63		0x3
555 
556 #define SW_REV_ID_M			GENMASK(7, 4)
557 
558 /* KSZ9893, KSZ9563, KSZ8563 specific register  */
559 #define REG_CHIP_ID4			0x0f
560 #define SKU_ID_KSZ8563			0x3c
561 
562 /* Driver set switch broadcast storm protection at 10% rate. */
563 #define BROADCAST_STORM_PROT_RATE	10
564 
565 /* 148,800 frames * 67 ms / 100 */
566 #define BROADCAST_STORM_VALUE		9969
567 
568 #define BROADCAST_STORM_RATE_HI		0x07
569 #define BROADCAST_STORM_RATE_LO		0xFF
570 #define BROADCAST_STORM_RATE		0x07FF
571 
572 #define MULTICAST_STORM_DISABLE		BIT(6)
573 
574 #define SW_START			0x01
575 
576 /* xMII configuration */
577 #define P_MII_DUPLEX_M			BIT(6)
578 #define P_MII_100MBIT_M			BIT(4)
579 
580 #define P_GMII_1GBIT_M			BIT(6)
581 #define P_RGMII_ID_IG_ENABLE		BIT(4)
582 #define P_RGMII_ID_EG_ENABLE		BIT(3)
583 #define P_MII_MAC_MODE			BIT(2)
584 #define P_MII_SEL_M			0x3
585 
586 /* Interrupt */
587 #define REG_SW_PORT_INT_STATUS__1	0x001B
588 #define REG_SW_PORT_INT_MASK__1		0x001F
589 
590 #define REG_PORT_INT_STATUS		0x001B
591 #define REG_PORT_INT_MASK		0x001F
592 
593 #define PORT_SRC_PHY_INT		1
594 
595 /* Regmap tables generation */
596 #define KSZ_SPI_OP_RD		3
597 #define KSZ_SPI_OP_WR		2
598 
599 #define swabnot_used(x)		0
600 
601 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad)		\
602 	swab##swp((opcode) << ((regbits) + (regpad)))
603 
604 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign)		\
605 	{								\
606 		.name = #width,						\
607 		.val_bits = (width),					\
608 		.reg_stride = 1,					\
609 		.reg_bits = (regbits) + (regalign),			\
610 		.pad_bits = (regpad),					\
611 		.max_register = BIT(regbits) - 1,			\
612 		.cache_type = REGCACHE_NONE,				\
613 		.read_flag_mask =					\
614 			KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp,	\
615 					     regbits, regpad),		\
616 		.write_flag_mask =					\
617 			KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp,	\
618 					     regbits, regpad),		\
619 		.lock = ksz_regmap_lock,				\
620 		.unlock = ksz_regmap_unlock,				\
621 		.reg_format_endian = REGMAP_ENDIAN_BIG,			\
622 		.val_format_endian = REGMAP_ENDIAN_BIG			\
623 	}
624 
625 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign)		\
626 	static const struct regmap_config ksz##_regmap_config[] = {	\
627 		KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \
628 		KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \
629 		KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \
630 	}
631 
632 #endif
633