1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
3 */
4
5 #ifndef UFS_QCOM_H_
6 #define UFS_QCOM_H_
7
8 #include <linux/reset-controller.h>
9 #include <linux/reset.h>
10 #include <ufs/ufshcd.h>
11
12 #define MAX_UFS_QCOM_HOSTS 1
13 #define MAX_U32 (~(u32)0)
14 #define MPHY_TX_FSM_STATE 0x41
15 #define TX_FSM_HIBERN8 0x1
16 #define HBRN8_POLL_TOUT_MS 100
17 #define DEFAULT_CLK_RATE_HZ 1000000
18 #define BUS_VECTOR_NAME_LEN 32
19 #define MAX_SUPP_MAC 64
20
21 #define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28)
22 #define UFS_HW_VER_MINOR_MASK GENMASK(27, 16)
23 #define UFS_HW_VER_STEP_MASK GENMASK(15, 0)
24
25 /* vendor specific pre-defined parameters */
26 #define SLOW 1
27 #define FAST 2
28
29 #define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B
30
31 /* QCOM UFS host controller vendor specific registers */
32 enum {
33 REG_UFS_SYS1CLK_1US = 0xC0,
34 REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4,
35 REG_UFS_LOCAL_PORT_ID_REG = 0xC8,
36 REG_UFS_PA_ERR_CODE = 0xCC,
37 /* On older UFS revisions, this register is called "RETRY_TIMER_REG" */
38 REG_UFS_PARAM0 = 0xD0,
39 /* On older UFS revisions, this register is called "REG_UFS_PA_LINK_STARTUP_TIMER" */
40 REG_UFS_CFG0 = 0xD8,
41 REG_UFS_CFG1 = 0xDC,
42 REG_UFS_CFG2 = 0xE0,
43 REG_UFS_HW_VERSION = 0xE4,
44
45 UFS_TEST_BUS = 0xE8,
46 UFS_TEST_BUS_CTRL_0 = 0xEC,
47 UFS_TEST_BUS_CTRL_1 = 0xF0,
48 UFS_TEST_BUS_CTRL_2 = 0xF4,
49 UFS_UNIPRO_CFG = 0xF8,
50
51 /*
52 * QCOM UFS host controller vendor specific registers
53 * added in HW Version 3.0.0
54 */
55 UFS_AH8_CFG = 0xFC,
56
57 REG_UFS_CFG3 = 0x271C,
58 };
59
60 /* QCOM UFS host controller vendor specific debug registers */
61 enum {
62 UFS_DBG_RD_REG_UAWM = 0x100,
63 UFS_DBG_RD_REG_UARM = 0x200,
64 UFS_DBG_RD_REG_TXUC = 0x300,
65 UFS_DBG_RD_REG_RXUC = 0x400,
66 UFS_DBG_RD_REG_DFC = 0x500,
67 UFS_DBG_RD_REG_TRLUT = 0x600,
68 UFS_DBG_RD_REG_TMRLUT = 0x700,
69 UFS_UFS_DBG_RD_REG_OCSC = 0x800,
70
71 UFS_UFS_DBG_RD_DESC_RAM = 0x1500,
72 UFS_UFS_DBG_RD_PRDT_RAM = 0x1700,
73 UFS_UFS_DBG_RD_RESP_RAM = 0x1800,
74 UFS_UFS_DBG_RD_EDTL_RAM = 0x1900,
75 };
76
77 enum {
78 UFS_MEM_CQIS_VS = 0x8,
79 };
80
81 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x)
82 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x)
83
84 /* bit definitions for REG_UFS_CFG0 register */
85 #define QUNIPRO_G4_SEL BIT(5)
86
87 /* bit definitions for REG_UFS_CFG1 register */
88 #define QUNIPRO_SEL BIT(0)
89 #define UFS_PHY_SOFT_RESET BIT(1)
90 #define UTP_DBG_RAMS_EN BIT(17)
91 #define TEST_BUS_EN BIT(18)
92 #define TEST_BUS_SEL GENMASK(22, 19)
93 #define UFS_REG_TEST_BUS_EN BIT(30)
94
95 #define UFS_PHY_RESET_ENABLE 1
96 #define UFS_PHY_RESET_DISABLE 0
97
98 /* bit definitions for REG_UFS_CFG2 register */
99 #define UAWM_HW_CGC_EN BIT(0)
100 #define UARM_HW_CGC_EN BIT(1)
101 #define TXUC_HW_CGC_EN BIT(2)
102 #define RXUC_HW_CGC_EN BIT(3)
103 #define DFC_HW_CGC_EN BIT(4)
104 #define TRLUT_HW_CGC_EN BIT(5)
105 #define TMRLUT_HW_CGC_EN BIT(6)
106 #define OCSC_HW_CGC_EN BIT(7)
107
108 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
109 #define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */
110
111 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\
112 TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\
113 DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\
114 TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN)
115
116 /* bit offset */
117 #define OFFSET_CLK_NS_REG 0xa
118
119 /* bit masks */
120 #define MASK_TX_SYMBOL_CLK_1US_REG GENMASK(9, 0)
121 #define MASK_CLK_NS_REG GENMASK(23, 10)
122
123 /* QUniPro Vendor specific attributes */
124 #define PA_VS_CONFIG_REG1 0x9000
125 #define DME_VS_CORE_CLK_CTRL 0xD002
126 /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
127 #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8)
128 #define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK 0xFF
129
130 static inline void
ufs_qcom_get_controller_revision(struct ufs_hba * hba,u8 * major,u16 * minor,u16 * step)131 ufs_qcom_get_controller_revision(struct ufs_hba *hba,
132 u8 *major, u16 *minor, u16 *step)
133 {
134 u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
135
136 *major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver);
137 *minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver);
138 *step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver);
139 };
140
ufs_qcom_assert_reset(struct ufs_hba * hba)141 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
142 {
143 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_ENABLE),
144 REG_UFS_CFG1);
145
146 /*
147 * Make sure assertion of ufs phy reset is written to
148 * register before returning
149 */
150 mb();
151 }
152
ufs_qcom_deassert_reset(struct ufs_hba * hba)153 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
154 {
155 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_DISABLE),
156 REG_UFS_CFG1);
157
158 /*
159 * Make sure de-assertion of ufs phy reset is written to
160 * register before returning
161 */
162 mb();
163 }
164
165 /* Host controller hardware version: major.minor.step */
166 struct ufs_hw_version {
167 u16 step;
168 u16 minor;
169 u8 major;
170 };
171
172 struct ufs_qcom_testbus {
173 u8 select_major;
174 u8 select_minor;
175 };
176
177 struct gpio_desc;
178
179 struct ufs_qcom_host {
180 /*
181 * Set this capability if host controller supports the QUniPro mode
182 * and if driver wants the Host controller to operate in QUniPro mode.
183 * Note: By default this capability will be kept enabled if host
184 * controller supports the QUniPro mode.
185 */
186 #define UFS_QCOM_CAP_QUNIPRO 0x1
187
188 /*
189 * Set this capability if host controller can retain the secure
190 * configuration even after UFS controller core power collapse.
191 */
192 #define UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE 0x2
193 u32 caps;
194
195 struct phy *generic_phy;
196 struct ufs_hba *hba;
197 struct ufs_pa_layer_attr dev_req_params;
198 struct clk *rx_l0_sync_clk;
199 struct clk *tx_l0_sync_clk;
200 struct clk *rx_l1_sync_clk;
201 struct clk *tx_l1_sync_clk;
202 bool is_lane_clks_enabled;
203
204 void __iomem *dev_ref_clk_ctrl_mmio;
205 bool is_dev_ref_clk_enabled;
206 struct ufs_hw_version hw_ver;
207 #ifdef CONFIG_SCSI_UFS_CRYPTO
208 void __iomem *ice_mmio;
209 #endif
210
211 u32 dev_ref_clk_en_mask;
212
213 struct ufs_qcom_testbus testbus;
214
215 /* Reset control of HCI */
216 struct reset_control *core_reset;
217 struct reset_controller_dev rcdev;
218
219 struct gpio_desc *device_reset;
220
221 int esi_base;
222 bool esi_enabled;
223 };
224
225 static inline u32
ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host * host,u32 reg)226 ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg)
227 {
228 if (host->hw_ver.major <= 0x02)
229 return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg);
230
231 return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg);
232 };
233
234 #define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba)
235 #define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba)
236 #define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba)
237
238 int ufs_qcom_testbus_config(struct ufs_qcom_host *host);
239
ufs_qcom_cap_qunipro(struct ufs_qcom_host * host)240 static inline bool ufs_qcom_cap_qunipro(struct ufs_qcom_host *host)
241 {
242 return host->caps & UFS_QCOM_CAP_QUNIPRO;
243 }
244
245 /* ufs-qcom-ice.c */
246
247 #ifdef CONFIG_SCSI_UFS_CRYPTO
248 int ufs_qcom_ice_init(struct ufs_qcom_host *host);
249 int ufs_qcom_ice_enable(struct ufs_qcom_host *host);
250 int ufs_qcom_ice_resume(struct ufs_qcom_host *host);
251 int ufs_qcom_ice_program_key(struct ufs_hba *hba,
252 const union ufs_crypto_cfg_entry *cfg, int slot);
253 #else
ufs_qcom_ice_init(struct ufs_qcom_host * host)254 static inline int ufs_qcom_ice_init(struct ufs_qcom_host *host)
255 {
256 return 0;
257 }
ufs_qcom_ice_enable(struct ufs_qcom_host * host)258 static inline int ufs_qcom_ice_enable(struct ufs_qcom_host *host)
259 {
260 return 0;
261 }
ufs_qcom_ice_resume(struct ufs_qcom_host * host)262 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
263 {
264 return 0;
265 }
266 #define ufs_qcom_ice_program_key NULL
267 #endif /* !CONFIG_SCSI_UFS_CRYPTO */
268
269 #endif /* UFS_QCOM_H_ */
270