Lines Matching full:arm

7 title: ARM L2 Cache Controller
13   ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/
34           - arm,pl310-cache
35           - arm,l220-cache
36           - arm,l210-cache
44             # compatible with the ARM one, with system cache mode (meaning
49             # compatible with the ARM one with outer cache mode.
53            # with arm,pl310-cache controller.
55           - const: arm,pl310-cache
69   arm,data-latency:
80   arm,tag-latency:
92   arm,dirty-latency:
98   arm,filter-ranges:
107   arm,io-coherent:
109       I/O coherent mode. Valid only when the arm,pl310-cache compatible
127   arm,double-linefill:
133   arm,double-linefill-incr:
139   arm,double-linefill-wrap:
145   arm,prefetch-drop:
151   arm,prefetch-offset:
156   arm,shared-override:
165   arm,parity-enable:
169   arm,parity-disable:
177   arm,outer-sync-disable:
179       Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
198   arm,dynamic-clock-gating:
206   arm,standby-mode:
213   arm,early-bresp-disable:
217   arm,full-line-zero-disable:
232         compatible = "arm,pl310-cache";
234         arm,data-latency = <1 1 1>;
235         arm,tag-latency = <2 2 2>;
236         arm,filter-ranges = <0x80000000 0x8000000>;