Lines Matching +full:vdds +full:- +full:supply
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7180-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
27 - description: Display core clock
29 clock-names:
31 - const: iface
32 - const: ahb
33 - const: core
41 interconnect-names:
45 "^display-controller@[0-9a-f]+$":
49 const: qcom,sc7180-dpu
51 "^displayport-controller@[0-9a-f]+$":
55 const: qcom,sc7180-dp
57 "^dsi@[0-9a-f]+$":
62 - const: qcom,sc7180-dsi-ctrl
63 - const: qcom,mdss-dsi-ctrl
65 "^phy@[0-9a-f]+$":
69 const: qcom,dsi-phy-10nm
72 - compatible
77 - |
78 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
79 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
80 #include <dt-bindings/clock/qcom,rpmh.h>
81 #include <dt-bindings/interrupt-controller/arm-gic.h>
82 #include <dt-bindings/interconnect/qcom,sdm845.h>
83 #include <dt-bindings/power/qcom-rpmpd.h>
85 display-subsystem@ae00000 {
86 #address-cells = <1>;
87 #size-cells = <1>;
88 compatible = "qcom,sc7180-mdss";
90 reg-names = "mdss";
91 power-domains = <&dispcc MDSS_GDSC>;
95 clock-names = "iface", "ahb", "core";
98 interrupt-controller;
99 #interrupt-cells = <1>;
102 interconnect-names = "mdp0-mem";
107 display-controller@ae01000 {
108 compatible = "qcom,sc7180-dpu";
112 reg-names = "mdp", "vbif";
120 clock-names = "bus", "iface", "rot", "lut", "core",
123 interrupt-parent = <&mdss>;
125 power-domains = <&rpmhpd SC7180_CX>;
126 operating-points-v2 = <&mdp_opp_table>;
129 #address-cells = <1>;
130 #size-cells = <0>;
135 remote-endpoint = <&dsi0_in>;
142 remote-endpoint = <&dp_in>;
149 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
151 reg-names = "dsi_ctrl";
153 interrupt-parent = <&mdss>;
162 clock-names = "byte",
169 … assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
170 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
172 operating-points-v2 = <&dsi_opp_table>;
173 power-domains = <&rpmhpd SC7180_CX>;
176 phy-names = "dsi";
178 #address-cells = <1>;
179 #size-cells = <0>;
182 #address-cells = <1>;
183 #size-cells = <0>;
188 remote-endpoint = <&dpu_intf1_out>;
199 dsi_opp_table: opp-table {
200 compatible = "operating-points-v2";
202 opp-187500000 {
203 opp-hz = /bits/ 64 <187500000>;
204 required-opps = <&rpmhpd_opp_low_svs>;
207 opp-300000000 {
208 opp-hz = /bits/ 64 <300000000>;
209 required-opps = <&rpmhpd_opp_svs>;
212 opp-358000000 {
213 opp-hz = /bits/ 64 <358000000>;
214 required-opps = <&rpmhpd_opp_svs_l1>;
220 compatible = "qcom,dsi-phy-10nm";
224 reg-names = "dsi_phy",
228 #clock-cells = <1>;
229 #phy-cells = <0>;
233 clock-names = "iface", "ref";
234 vdds-supply = <&vreg_dsi_phy>;
237 displayport-controller@ae90000 {
238 compatible = "qcom,sc7180-dp";
246 interrupt-parent = <&mdss>;
254 clock-names = "core_iface", "core_aux", "ctrl_link",
256 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
258 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
260 phy-names = "dp";
262 operating-points-v2 = <&dp_opp_table>;
263 power-domains = <&rpmhpd SC7180_CX>;
265 #sound-dai-cells = <0>;
268 #address-cells = <1>;
269 #size-cells = <0>;
273 remote-endpoint = <&dpu_intf0_out>;
283 dp_opp_table: opp-table {
284 compatible = "operating-points-v2";
286 opp-160000000 {
287 opp-hz = /bits/ 64 <160000000>;
288 required-opps = <&rpmhpd_opp_low_svs>;
291 opp-270000000 {
292 opp-hz = /bits/ 64 <270000000>;
293 required-opps = <&rpmhpd_opp_svs>;
296 opp-540000000 {
297 opp-hz = /bits/ 64 <540000000>;
298 required-opps = <&rpmhpd_opp_svs_l1>;
301 opp-810000000 {
302 opp-hz = /bits/ 64 <810000000>;
303 required-opps = <&rpmhpd_opp_nom>;