Lines Matching +full:0 +full:x24000
36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
60 pattern: "^(pruss|icssg)@[0-9a-f]+$"
65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
161 const: 0
175 const: 0
209 const: 0
297 "^(pru|rtu|txpru)@[0-9a-f]+$":
350 pruss: pruss@0 {
352 reg = <0x0 0x80000>;
357 pruss_mem: memories@0 {
358 reg = <0x0 0x2000>,
359 <0x2000 0x2000>,
360 <0x10000 0x3000>;
368 reg = <0x26000 0x2000>;
369 ranges = <0x00 0x26000 0x2000>;
373 #size-cells = <0>;
376 reg = <0x30>;
377 #clock-cells = <0>;
386 reg = <0x32000 0x58>;
391 reg = <0x20000 0x2000>;
403 reg = <0x34000 0x2000>,
404 <0x22000 0x400>,
405 <0x22400 0x100>;
412 reg = <0x38000 0x2000>,
413 <0x24000 0x400>,
414 <0x24400 0x100>;
421 reg = <0x32400 0x90>;
426 #size-cells = <0>;
434 pruss1: pruss@0 {
436 reg = <0x0 0x40000>;
441 pruss1_mem: memories@0 {
442 reg = <0x0 0x2000>,
443 <0x2000 0x2000>,
444 <0x10000 0x8000>;
452 reg = <0x26000 0x2000>;
453 ranges = <0x00 0x26000 0x2000>;
457 #size-cells = <0>;
460 reg = <0x30>;
461 #clock-cells = <0>;
470 reg = <0x32000 0x58>;
475 reg = <0x20000 0x2000>;
489 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
494 reg = <0x34000 0x3000>,
495 <0x22000 0x400>,
496 <0x22400 0x100>;
503 reg = <0x38000 0x3000>,
504 <0x24000 0x400>,
505 <0x24400 0x100>;
512 reg = <0x32400 0x90>;
517 #size-cells = <0>;