Lines Matching +full:spi +full:- +full:max +full:- +full:frequency
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra114-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra114 SPI controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - const: nvidia,tegra114-spi
17 - items:
18 - enum:
19 - nvidia,tegra210-spi
20 - nvidia,tegra124-spi
21 - const: nvidia,tegra114-spi
31 - description: SPI module clock
33 clock-names:
35 - const: spi
39 - description: SPI module reset
41 reset-names:
43 - const: spi
47 - description: DMA channel for the reception FIFO
48 - description: DMA channel for the transmission FIFO
50 dma-names:
52 - const: rx
53 - const: tx
55 spi-max-frequency:
56 description: Maximum SPI clocking speed of the controller in Hz.
60 - $ref: spi-controller.yaml
65 - compatible
66 - reg
67 - interrupts
68 - clocks
69 - clock-names
70 - resets
71 - reset-names
72 - dmas
73 - dma-names
76 - |
77 spi@7000d600 {
78 compatible = "nvidia,tegra114-spi";
82 clock-names = "spi";
84 reset-names = "spi";
86 dma-names = "rx", "tx";
88 spi-max-frequency = <25000000>;
90 #address-cells = <1>;
91 #size-cells = <0>;
94 compatible = "jedec,spi-nor";
96 spi-max-frequency = <20000000>;
97 nvidia,rx-clk-tap-delay = <0>;
98 nvidia,tx-clk-tap-delay = <16>;