Lines Matching refs:r5
78 ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
79 bic r5, r5, #PDE_BIT & 0xff
80 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
83 and r5, r5, #PWD_EN_BIT & 0xff
84 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
87 ldr r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
88 orr r5, r5, #SELF_REFRESH_MODE & 0xff000000
89 orr r5, r5, #SELF_REFRESH_MODE & 0x000000ff
90 str r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
93 ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
94 orr r5, r5, #IDLE_EMIFS_REQUEST & 0xff
95 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
103 mov r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff
104 orr r5, r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
105 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
112 mov r5, #IDLE_WAIT_CYCLES & 0xff
113 orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
115 subs r5, r5, #1
174 mov r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff
175 orr r5, r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff00
176 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]