Lines Matching refs:val
61 static void __gic_v3_set_lr(u64 val, int lr) in __gic_v3_set_lr() argument
65 write_gicreg(val, ICH_LR0_EL2); in __gic_v3_set_lr()
68 write_gicreg(val, ICH_LR1_EL2); in __gic_v3_set_lr()
71 write_gicreg(val, ICH_LR2_EL2); in __gic_v3_set_lr()
74 write_gicreg(val, ICH_LR3_EL2); in __gic_v3_set_lr()
77 write_gicreg(val, ICH_LR4_EL2); in __gic_v3_set_lr()
80 write_gicreg(val, ICH_LR5_EL2); in __gic_v3_set_lr()
83 write_gicreg(val, ICH_LR6_EL2); in __gic_v3_set_lr()
86 write_gicreg(val, ICH_LR7_EL2); in __gic_v3_set_lr()
89 write_gicreg(val, ICH_LR8_EL2); in __gic_v3_set_lr()
92 write_gicreg(val, ICH_LR9_EL2); in __gic_v3_set_lr()
95 write_gicreg(val, ICH_LR10_EL2); in __gic_v3_set_lr()
98 write_gicreg(val, ICH_LR11_EL2); in __gic_v3_set_lr()
101 write_gicreg(val, ICH_LR12_EL2); in __gic_v3_set_lr()
104 write_gicreg(val, ICH_LR13_EL2); in __gic_v3_set_lr()
107 write_gicreg(val, ICH_LR14_EL2); in __gic_v3_set_lr()
110 write_gicreg(val, ICH_LR15_EL2); in __gic_v3_set_lr()
115 static void __vgic_v3_write_ap0rn(u32 val, int n) in __vgic_v3_write_ap0rn() argument
119 write_gicreg(val, ICH_AP0R0_EL2); in __vgic_v3_write_ap0rn()
122 write_gicreg(val, ICH_AP0R1_EL2); in __vgic_v3_write_ap0rn()
125 write_gicreg(val, ICH_AP0R2_EL2); in __vgic_v3_write_ap0rn()
128 write_gicreg(val, ICH_AP0R3_EL2); in __vgic_v3_write_ap0rn()
133 static void __vgic_v3_write_ap1rn(u32 val, int n) in __vgic_v3_write_ap1rn() argument
137 write_gicreg(val, ICH_AP1R0_EL2); in __vgic_v3_write_ap1rn()
140 write_gicreg(val, ICH_AP1R1_EL2); in __vgic_v3_write_ap1rn()
143 write_gicreg(val, ICH_AP1R2_EL2); in __vgic_v3_write_ap1rn()
146 write_gicreg(val, ICH_AP1R3_EL2); in __vgic_v3_write_ap1rn()
153 u32 val; in __vgic_v3_read_ap0rn() local
157 val = read_gicreg(ICH_AP0R0_EL2); in __vgic_v3_read_ap0rn()
160 val = read_gicreg(ICH_AP0R1_EL2); in __vgic_v3_read_ap0rn()
163 val = read_gicreg(ICH_AP0R2_EL2); in __vgic_v3_read_ap0rn()
166 val = read_gicreg(ICH_AP0R3_EL2); in __vgic_v3_read_ap0rn()
172 return val; in __vgic_v3_read_ap0rn()
177 u32 val; in __vgic_v3_read_ap1rn() local
181 val = read_gicreg(ICH_AP1R0_EL2); in __vgic_v3_read_ap1rn()
184 val = read_gicreg(ICH_AP1R1_EL2); in __vgic_v3_read_ap1rn()
187 val = read_gicreg(ICH_AP1R2_EL2); in __vgic_v3_read_ap1rn()
190 val = read_gicreg(ICH_AP1R3_EL2); in __vgic_v3_read_ap1rn()
196 return val; in __vgic_v3_read_ap1rn()
309 u64 val; in __vgic_v3_deactivate_traps() local
315 val = read_gicreg(ICC_SRE_EL2); in __vgic_v3_deactivate_traps()
316 write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2); in __vgic_v3_deactivate_traps()
335 u64 val; in __vgic_v3_save_aprs() local
338 val = read_gicreg(ICH_VTR_EL2); in __vgic_v3_save_aprs()
339 nr_pre_bits = vtr_to_nr_pre_bits(val); in __vgic_v3_save_aprs()
368 u64 val; in __vgic_v3_restore_aprs() local
371 val = read_gicreg(ICH_VTR_EL2); in __vgic_v3_restore_aprs()
372 nr_pre_bits = vtr_to_nr_pre_bits(val); in __vgic_v3_restore_aprs()
416 u64 val, sre = read_gicreg(ICC_SRE_EL1); in __vgic_v3_get_gic_config() local
442 val = read_gicreg(ICC_SRE_EL1); in __vgic_v3_get_gic_config()
452 val = (val & ICC_SRE_EL1_SRE) ? 0 : (1ULL << 63); in __vgic_v3_get_gic_config()
453 val |= read_gicreg(ICH_VTR_EL2); in __vgic_v3_get_gic_config()
455 return val; in __vgic_v3_get_gic_config()
511 u64 val = __gic_v3_get_lr(i); in __vgic_v3_highest_priority_lr() local
512 u8 lr_prio = (val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT; in __vgic_v3_highest_priority_lr()
515 if ((val & ICH_LR_STATE) != ICH_LR_PENDING_BIT) in __vgic_v3_highest_priority_lr()
519 if (!(val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG0_MASK)) in __vgic_v3_highest_priority_lr()
523 if ((val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG1_MASK)) in __vgic_v3_highest_priority_lr()
532 *lr_val = val; in __vgic_v3_highest_priority_lr()
549 u64 val = __gic_v3_get_lr(i); in __vgic_v3_find_active_lr() local
551 if ((val & ICH_LR_VIRTUAL_ID_MASK) == intid && in __vgic_v3_find_active_lr()
552 (val & ICH_LR_ACTIVE_BIT)) { in __vgic_v3_find_active_lr()
553 *lr_val = val; in __vgic_v3_find_active_lr()
569 u32 val; in __vgic_v3_get_highest_active_priority() local
581 val = __vgic_v3_read_ap0rn(i); in __vgic_v3_get_highest_active_priority()
582 val |= __vgic_v3_read_ap1rn(i); in __vgic_v3_get_highest_active_priority()
583 if (!val) { in __vgic_v3_get_highest_active_priority()
588 return (hap + __ffs(val)) << __vgic_v3_bpr_min(); in __vgic_v3_get_highest_active_priority()
639 u32 val; in __vgic_v3_set_active_priority() local
647 val = __vgic_v3_read_ap0rn(apr); in __vgic_v3_set_active_priority()
648 __vgic_v3_write_ap0rn(val | BIT(ap % 32), apr); in __vgic_v3_set_active_priority()
650 val = __vgic_v3_read_ap1rn(apr); in __vgic_v3_set_active_priority()
651 __vgic_v3_write_ap1rn(val | BIT(ap % 32), apr); in __vgic_v3_set_active_priority()
819 u64 val = vcpu_get_reg(vcpu, rt); in __vgic_v3_write_igrpen0() local
821 if (val & 1) in __vgic_v3_write_igrpen0()
831 u64 val = vcpu_get_reg(vcpu, rt); in __vgic_v3_write_igrpen1() local
833 if (val & 1) in __vgic_v3_write_igrpen1()
853 u64 val = vcpu_get_reg(vcpu, rt); in __vgic_v3_write_bpr0() local
857 if (val < bpr_min) in __vgic_v3_write_bpr0()
858 val = bpr_min; in __vgic_v3_write_bpr0()
860 val <<= ICH_VMCR_BPR0_SHIFT; in __vgic_v3_write_bpr0()
861 val &= ICH_VMCR_BPR0_MASK; in __vgic_v3_write_bpr0()
863 vmcr |= val; in __vgic_v3_write_bpr0()
870 u64 val = vcpu_get_reg(vcpu, rt); in __vgic_v3_write_bpr1() local
877 if (val < bpr_min) in __vgic_v3_write_bpr1()
878 val = bpr_min; in __vgic_v3_write_bpr1()
880 val <<= ICH_VMCR_BPR1_SHIFT; in __vgic_v3_write_bpr1()
881 val &= ICH_VMCR_BPR1_MASK; in __vgic_v3_write_bpr1()
883 vmcr |= val; in __vgic_v3_write_bpr1()
890 u32 val; in __vgic_v3_read_apxrn() local
893 val = __vgic_v3_read_ap0rn(n); in __vgic_v3_read_apxrn()
895 val = __vgic_v3_read_ap1rn(n); in __vgic_v3_read_apxrn()
897 vcpu_set_reg(vcpu, rt, val); in __vgic_v3_read_apxrn()
902 u32 val = vcpu_get_reg(vcpu, rt); in __vgic_v3_write_apxrn() local
905 __vgic_v3_write_ap0rn(val, n); in __vgic_v3_write_apxrn()
907 __vgic_v3_write_ap1rn(val, n); in __vgic_v3_write_apxrn()
980 u32 val = vcpu_get_reg(vcpu, rt); in __vgic_v3_write_pmr() local
982 val <<= ICH_VMCR_PMR_SHIFT; in __vgic_v3_write_pmr()
983 val &= ICH_VMCR_PMR_MASK; in __vgic_v3_write_pmr()
985 vmcr |= val; in __vgic_v3_write_pmr()
992 u32 val = __vgic_v3_get_highest_active_priority(); in __vgic_v3_read_rpr() local
993 vcpu_set_reg(vcpu, rt, val); in __vgic_v3_read_rpr()
998 u32 vtr, val; in __vgic_v3_read_ctlr() local
1002 val = ((vtr >> 29) & 7) << ICC_CTLR_EL1_PRI_BITS_SHIFT; in __vgic_v3_read_ctlr()
1004 val |= ((vtr >> 23) & 7) << ICC_CTLR_EL1_ID_BITS_SHIFT; in __vgic_v3_read_ctlr()
1007 val |= BIT(ICC_CTLR_EL1_SEIS_SHIFT); in __vgic_v3_read_ctlr()
1009 val |= ((vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT; in __vgic_v3_read_ctlr()
1011 val |= ((vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT) << ICC_CTLR_EL1_EOImode_SHIFT; in __vgic_v3_read_ctlr()
1013 val |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT; in __vgic_v3_read_ctlr()
1015 vcpu_set_reg(vcpu, rt, val); in __vgic_v3_read_ctlr()
1020 u32 val = vcpu_get_reg(vcpu, rt); in __vgic_v3_write_ctlr() local
1022 if (val & ICC_CTLR_EL1_CBPR_MASK) in __vgic_v3_write_ctlr()
1027 if (val & ICC_CTLR_EL1_EOImode_MASK) in __vgic_v3_write_ctlr()