14 			u64 val)  in set_gic_ctlr()  argument
26 	host_pri_bits = FIELD_GET(ICC_CTLR_EL1_PRI_BITS_MASK, val) + 1;  in set_gic_ctlr()
32 	host_id_bits = FIELD_GET(ICC_CTLR_EL1_ID_BITS_MASK, val);  in set_gic_ctlr()
39 	seis = FIELD_GET(ICC_CTLR_EL1_SEIS_MASK, val);  in set_gic_ctlr()
44 	a3v = FIELD_GET(ICC_CTLR_EL1_A3V_MASK, val);  in set_gic_ctlr()
52 	vmcr.cbpr = FIELD_GET(ICC_CTLR_EL1_CBPR_MASK, val);  in set_gic_ctlr()
53 	vmcr.eoim = FIELD_GET(ICC_CTLR_EL1_EOImode_MASK, val);  in set_gic_ctlr()
64 	u64 val;  in get_gic_ctlr()  local
67 	val = 0;  in get_gic_ctlr()
68 	val |= FIELD_PREP(ICC_CTLR_EL1_PRI_BITS_MASK, vgic_v3_cpu->num_pri_bits - 1);  in get_gic_ctlr()
69 	val |= FIELD_PREP(ICC_CTLR_EL1_ID_BITS_MASK, vgic_v3_cpu->num_id_bits);  in get_gic_ctlr()
70 	val |= FIELD_PREP(ICC_CTLR_EL1_SEIS_MASK,  in get_gic_ctlr()
73 	val |= FIELD_PREP(ICC_CTLR_EL1_A3V_MASK,  in get_gic_ctlr()
79 	val |= FIELD_PREP(ICC_CTLR_EL1_CBPR_MASK, vmcr.cbpr);  in get_gic_ctlr()
80 	val |= FIELD_PREP(ICC_CTLR_EL1_EOImode_MASK, vmcr.eoim);  in get_gic_ctlr()
82 	*valp = val;  in get_gic_ctlr()
88 		       u64 val)  in set_gic_pmr()  argument
93 	vmcr.pmr = FIELD_GET(ICC_PMR_EL1_MASK, val);  in set_gic_pmr()
100 		       u64 *val)  in get_gic_pmr()  argument
105 	*val = FIELD_PREP(ICC_PMR_EL1_MASK, vmcr.pmr);  in get_gic_pmr()
111 			u64 val)  in set_gic_bpr0()  argument
116 	vmcr.bpr = FIELD_GET(ICC_BPR0_EL1_MASK, val);  in set_gic_bpr0()
123 			u64 *val)  in get_gic_bpr0()  argument
128 	*val = FIELD_PREP(ICC_BPR0_EL1_MASK, vmcr.bpr);  in get_gic_bpr0()
134 			u64 val)  in set_gic_bpr1()  argument
140 		vmcr.abpr = FIELD_GET(ICC_BPR1_EL1_MASK, val);  in set_gic_bpr1()
148 			u64 *val)  in get_gic_bpr1()  argument
154 		*val = FIELD_PREP(ICC_BPR1_EL1_MASK, vmcr.abpr);  in get_gic_bpr1()
156 		*val = min((vmcr.bpr + 1), 7U);  in get_gic_bpr1()
163 			  u64 val)  in set_gic_grpen0()  argument
168 	vmcr.grpen0 = FIELD_GET(ICC_IGRPEN0_EL1_MASK, val);  in set_gic_grpen0()
175 			  u64 *val)  in get_gic_grpen0()  argument
180 	*val = FIELD_PREP(ICC_IGRPEN0_EL1_MASK, vmcr.grpen0);  in get_gic_grpen0()
186 			  u64 val)  in set_gic_grpen1()  argument
191 	vmcr.grpen1 = FIELD_GET(ICC_IGRPEN1_EL1_MASK, val);  in set_gic_grpen1()
198 			  u64 *val)  in get_gic_grpen1()  argument
203 	*val = FIELD_GET(ICC_IGRPEN1_EL1_MASK, vmcr.grpen1);  in get_gic_grpen1()
208 static void set_apr_reg(struct kvm_vcpu *vcpu, u64 val, u8 apr, u8 idx)  in set_apr_reg()  argument
213 		vgicv3->vgic_ap1r[idx] = val;  in set_apr_reg()
215 		vgicv3->vgic_ap0r[idx] = val;  in set_apr_reg()
229 			u64 val)  in set_gic_ap0r()  argument
237 	set_apr_reg(vcpu, val, 0, idx);  in set_gic_ap0r()
242 			u64 *val)  in get_gic_ap0r()  argument
249 	*val = get_apr_reg(vcpu, 0, idx);  in get_gic_ap0r()
255 			u64 val)  in set_gic_ap1r()  argument
263 	set_apr_reg(vcpu, val, 1, idx);  in set_gic_ap1r()
268 			u64 *val)  in get_gic_ap1r()  argument
275 	*val = get_apr_reg(vcpu, 1, idx);  in get_gic_ap1r()
281 		       u64 val)  in set_gic_sre()  argument
284 	if (!(val & ICC_SRE_EL1_SRE))  in set_gic_sre()
291 		       u64 *val)  in get_gic_sre()  argument
295 	*val = vgicv3->vgic_sre;  in get_gic_sre()