Lines Matching refs:x86_spec_ctrl_base
54 u64 x86_spec_ctrl_base; variable
55 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
139 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); in cpu_select_mitigations()
146 x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK; in cpu_select_mitigations()
1556 x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S; in spec_ctrl_disable_kernel_rrsba()
1557 update_spec_ctrl(x86_spec_ctrl_base); in spec_ctrl_disable_kernel_rrsba()
1617 x86_spec_ctrl_base |= SPEC_CTRL_BHI_DIS_S; in spec_ctrl_bhi_dis()
1618 update_spec_ctrl(x86_spec_ctrl_base); in spec_ctrl_bhi_dis()
1750 x86_spec_ctrl_base |= SPEC_CTRL_IBRS; in spectre_v2_select_mitigation()
1751 update_spec_ctrl(x86_spec_ctrl_base); in spectre_v2_select_mitigation()
1868 u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP); in update_stibp_msr()
1875 u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; in update_stibp_strict()
1880 if (mask == x86_spec_ctrl_base) in update_stibp_strict()
1885 x86_spec_ctrl_base = mask; in update_stibp_strict()
2099 x86_spec_ctrl_base |= SPEC_CTRL_SSBD; in __ssb_select_mitigation()
2100 update_spec_ctrl(x86_spec_ctrl_base); in __ssb_select_mitigation()
2353 update_spec_ctrl(x86_spec_ctrl_base); in x86_spec_ctrl_setup_ap()