Lines Matching refs:dma_q
303 strtab->dma_q = IVPU_MMU_STRTAB_BASE_RA; in ivpu_mmu_strtab_alloc()
304 strtab->dma_q |= strtab->dma & IVPU_MMU_STRTAB_BASE_ADDR_MASK; in ivpu_mmu_strtab_alloc()
307 &strtab->dma, &strtab->dma_q, size); in ivpu_mmu_strtab_alloc()
321 q->dma_q = IVPU_MMU_Q_BASE_RWA; in ivpu_mmu_cmdq_alloc()
322 q->dma_q |= q->dma & IVPU_MMU_Q_BASE_ADDR_MASK; in ivpu_mmu_cmdq_alloc()
323 q->dma_q |= IVPU_MMU_Q_COUNT_LOG2; in ivpu_mmu_cmdq_alloc()
326 &q->dma, &q->dma_q, IVPU_MMU_CMDQ_SIZE); in ivpu_mmu_cmdq_alloc()
340 q->dma_q = IVPU_MMU_Q_BASE_RWA; in ivpu_mmu_evtq_alloc()
341 q->dma_q |= q->dma & IVPU_MMU_Q_BASE_ADDR_MASK; in ivpu_mmu_evtq_alloc()
342 q->dma_q |= IVPU_MMU_Q_COUNT_LOG2; in ivpu_mmu_evtq_alloc()
345 &q->dma, &q->dma_q, IVPU_MMU_EVTQ_SIZE); in ivpu_mmu_evtq_alloc()
509 REGV_WR64(VPU_37XX_HOST_MMU_STRTAB_BASE, mmu->strtab.dma_q); in ivpu_mmu_reset()
512 REGV_WR64(VPU_37XX_HOST_MMU_CMDQ_BASE, mmu->cmdq.dma_q); in ivpu_mmu_reset()
533 REGV_WR64(VPU_37XX_HOST_MMU_EVTQ_BASE, mmu->evtq.dma_q); in ivpu_mmu_reset()