3122 #undef ZERO
3123 #define ZERO(reg) writel(0, port_mmio + (reg))  macro
3131 	ZERO(0x028);	/* command */  in mv5_reset_hc_port()
3133 	ZERO(0x004);	/* timer */  in mv5_reset_hc_port()
3134 	ZERO(0x008);	/* irq err cause */  in mv5_reset_hc_port()
3135 	ZERO(0x00c);	/* irq err mask */  in mv5_reset_hc_port()
3136 	ZERO(0x010);	/* rq bah */  in mv5_reset_hc_port()
3137 	ZERO(0x014);	/* rq inp */  in mv5_reset_hc_port()
3138 	ZERO(0x018);	/* rq outp */  in mv5_reset_hc_port()
3139 	ZERO(0x01c);	/* respq bah */  in mv5_reset_hc_port()
3140 	ZERO(0x024);	/* respq outp */  in mv5_reset_hc_port()
3141 	ZERO(0x020);	/* respq inp */  in mv5_reset_hc_port()
3142 	ZERO(0x02c);	/* test control */  in mv5_reset_hc_port()
3145 #undef ZERO
3147 #define ZERO(reg) writel(0, hc_mmio + (reg))  macro
3154 	ZERO(0x00c);  in mv5_reset_one_hc()
3155 	ZERO(0x010);  in mv5_reset_one_hc()
3156 	ZERO(0x014);  in mv5_reset_one_hc()
3157 	ZERO(0x018);  in mv5_reset_one_hc()
3164 #undef ZERO
3183 #undef ZERO
3184 #define ZERO(reg) writel(0, mmio + (reg))  macro
3194 	ZERO(MV_PCI_DISC_TIMER);  in mv_reset_pci_bus()
3195 	ZERO(MV_PCI_MSI_TRIGGER);  in mv_reset_pci_bus()
3197 	ZERO(MV_PCI_SERR_MASK);  in mv_reset_pci_bus()
3198 	ZERO(hpriv->irq_cause_offset);  in mv_reset_pci_bus()
3199 	ZERO(hpriv->irq_mask_offset);  in mv_reset_pci_bus()
3200 	ZERO(MV_PCI_ERR_LOW_ADDRESS);  in mv_reset_pci_bus()
3201 	ZERO(MV_PCI_ERR_HIGH_ADDRESS);  in mv_reset_pci_bus()
3202 	ZERO(MV_PCI_ERR_ATTRIBUTE);  in mv_reset_pci_bus()
3203 	ZERO(MV_PCI_ERR_COMMAND);  in mv_reset_pci_bus()
3205 #undef ZERO
3405 #undef ZERO
3406 #define ZERO(reg) writel(0, port_mmio + (reg))  macro
3414 	ZERO(0x028);		/* command */  in mv_soc_reset_hc_port()
3416 	ZERO(0x004);		/* timer */  in mv_soc_reset_hc_port()
3417 	ZERO(0x008);		/* irq err cause */  in mv_soc_reset_hc_port()
3418 	ZERO(0x00c);		/* irq err mask */  in mv_soc_reset_hc_port()
3419 	ZERO(0x010);		/* rq bah */  in mv_soc_reset_hc_port()
3420 	ZERO(0x014);		/* rq inp */  in mv_soc_reset_hc_port()
3421 	ZERO(0x018);		/* rq outp */  in mv_soc_reset_hc_port()
3422 	ZERO(0x01c);		/* respq bah */  in mv_soc_reset_hc_port()
3423 	ZERO(0x024);		/* respq outp */  in mv_soc_reset_hc_port()
3424 	ZERO(0x020);		/* respq inp */  in mv_soc_reset_hc_port()
3425 	ZERO(0x02c);		/* test control */  in mv_soc_reset_hc_port()
3429 #undef ZERO
3431 #define ZERO(reg) writel(0, hc_mmio + (reg))  macro
3437 	ZERO(0x00c);  in mv_soc_reset_one_hc()
3438 	ZERO(0x010);  in mv_soc_reset_one_hc()
3439 	ZERO(0x014);  in mv_soc_reset_one_hc()
3443 #undef ZERO