Lines Matching refs:SPI_AVMM_VAL_SIZE
75 #define SPI_AVMM_VAL_SIZE 4UL macro
107 #define TRANS_WR_TX_SIZE(n) (TRANS_REQ_HD_SIZE + SPI_AVMM_VAL_SIZE * (n))
111 #define TRANS_RD_RX_SIZE(n) (SPI_AVMM_VAL_SIZE * (n))
202 header->size = cpu_to_be16((u16)count * SPI_AVMM_VAL_SIZE); in br_trans_tx_prepare()
208 trans_len += SPI_AVMM_VAL_SIZE * count; in br_trans_tx_prepare()
506 if (expected_count * SPI_AVMM_VAL_SIZE != trans_len) in br_rd_trans_rx_parse()
535 if (!val_len || val_len != expected_count * SPI_AVMM_VAL_SIZE) in br_wr_trans_rx_parse()
539 if ((val_len == SPI_AVMM_VAL_SIZE && code != TRANS_CODE_WRITE) || in br_wr_trans_rx_parse()
540 (val_len > SPI_AVMM_VAL_SIZE && code != TRANS_CODE_SEQ_WRITE)) in br_wr_trans_rx_parse()
585 if (!IS_ALIGNED(val_len, SPI_AVMM_VAL_SIZE)) in regmap_spi_avmm_gather_write()
589 val_len / SPI_AVMM_VAL_SIZE); in regmap_spi_avmm_gather_write()
594 if (bytes < SPI_AVMM_REG_SIZE + SPI_AVMM_VAL_SIZE) in regmap_spi_avmm_write()
609 if (!IS_ALIGNED(val_len, SPI_AVMM_VAL_SIZE)) in regmap_spi_avmm_read()
613 (val_len / SPI_AVMM_VAL_SIZE)); in regmap_spi_avmm_read()
662 .max_raw_read = SPI_AVMM_VAL_SIZE * MAX_READ_CNT,
663 .max_raw_write = SPI_AVMM_VAL_SIZE * MAX_WRITE_CNT,