Lines Matching refs:JH7110_SYSCLK_PLL0_OUT

33 #define JH7110_SYSCLK_PLL0_OUT			(JH7110_SYSCLK_END + 9)  macro
41 		    JH7110_SYSCLK_PLL0_OUT),
48 		    JH7110_SYSCLK_PLL0_OUT,
60 	JH71X0__DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2, JH7110_SYSCLK_PLL0_OUT),
144 	JH71X0_GDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 0, 7, JH7110_SYSCLK_PLL0_OUT),
168 	JH71X0__DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16, JH7110_SYSCLK_PLL0_OUT),
178 	JH71X0__DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15, JH7110_SYSCLK_PLL0_OUT),
184 	JH71X0__DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7, JH7110_SYSCLK_PLL0_OUT),
185 	JH71X0__DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15, JH7110_SYSCLK_PLL0_OUT),
200 	JH71X0_GDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk", 0, 15, JH7110_SYSCLK_PLL0_OUT),
481 			else if (pidx == JH7110_SYSCLK_PLL0_OUT && !priv->pll[0])  in jh7110_syscrg_probe()
488 				parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT];  in jh7110_syscrg_probe()