Lines Matching refs:offs
331 static inline u32 dfll_readl(struct tegra_dfll *td, u32 offs) in dfll_readl() argument
333 return __raw_readl(td->base + offs); in dfll_readl()
336 static inline void dfll_writel(struct tegra_dfll *td, u32 val, u32 offs) in dfll_writel() argument
338 WARN_ON(offs >= DFLL_I2C_CFG); in dfll_writel()
339 __raw_writel(val, td->base + offs); in dfll_writel()
349 static inline u32 dfll_i2c_readl(struct tegra_dfll *td, u32 offs) in dfll_i2c_readl() argument
351 return __raw_readl(td->i2c_base + offs); in dfll_i2c_readl()
354 static inline void dfll_i2c_writel(struct tegra_dfll *td, u32 val, u32 offs) in dfll_i2c_writel() argument
356 __raw_writel(val, td->i2c_base + offs); in dfll_i2c_writel()
1326 u32 val, offs; in attr_registers_show() local
1330 for (offs = 0; offs <= DFLL_MONITOR_DATA; offs += 4) { in attr_registers_show()
1331 if (offs == DFLL_OUTPUT_CFG) in attr_registers_show()
1332 val = dfll_i2c_readl(td, offs); in attr_registers_show()
1334 val = dfll_readl(td, offs); in attr_registers_show()
1335 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, val); in attr_registers_show()
1339 for (offs = DFLL_I2C_CFG; offs <= DFLL_I2C_STS; offs += 4) in attr_registers_show()
1340 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, in attr_registers_show()
1341 dfll_i2c_readl(td, offs)); in attr_registers_show()
1342 for (offs = DFLL_INTR_STS; offs <= DFLL_INTR_EN; offs += 4) in attr_registers_show()
1343 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, in attr_registers_show()
1344 dfll_i2c_readl(td, offs)); in attr_registers_show()
1348 offs = DFLL_I2C_CLK_DIVISOR; in attr_registers_show()
1349 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, in attr_registers_show()
1350 __raw_readl(td->i2c_controller_base + offs)); in attr_registers_show()
1353 for (offs = 0; offs < 4 * MAX_DFLL_VOLTAGES; offs += 4) in attr_registers_show()
1354 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, in attr_registers_show()
1355 __raw_readl(td->lut_base + offs)); in attr_registers_show()