36 static void __iomem *timer_base __ro_after_init;
43 	val = readl(timer_base + TPM_C0SC);  in tpm_timer_disable()
45 	writel(val, timer_base + TPM_C0SC);  in tpm_timer_disable()
53 	val = readl(timer_base + TPM_C0SC);  in tpm_timer_enable()
56 	writel(val, timer_base + TPM_C0SC);  in tpm_timer_enable()
61 	writel(TPM_STATUS_CH0F, timer_base + TPM_STATUS);  in tpm_irq_acknowledge()
66 	return readl(timer_base + TPM_CNT);  in tpm_read_counter()
90 	writel(next, timer_base + TPM_C0V);  in tpm_set_next_event()
158 	return clocksource_mmio_init(timer_base + TPM_CNT,  in tpm_clocksource_init()
197 	timer_base = timer_of_base(&to_tpm);  in tpm_timer_init()
199 	counter_width = (readl(timer_base + TPM_PARAM)  in tpm_timer_init()
213 	writel(0, timer_base + TPM_SC);  in tpm_timer_init()
215 	writel(TPM_SC_TOF_MASK, timer_base + TPM_SC);  in tpm_timer_init()
216 	writel(0, timer_base + TPM_CNT);  in tpm_timer_init()
218 	writel(TPM_C0SC_CHF_MASK, timer_base + TPM_C0SC);  in tpm_timer_init()
227 		timer_base + TPM_SC);  in tpm_timer_init()
230 	writel(GENMASK(counter_width - 1, 0), timer_base + TPM_MOD);  in tpm_timer_init()