Lines Matching defs:amd64_pvt
328 struct amd64_pvt { struct
329 struct low_ops *ops;
332 struct pci_dev *F1, *F2, *F3;
334 u16 mc_node_id; /* MC index of this MC node */
335 u8 fam; /* CPU family */
336 u8 model; /* ... model */
337 u8 stepping; /* ... stepping */
339 int ext_model; /* extended model value of this node */
342 u32 dclr0; /* DRAM Configuration Low DCT0 reg */
343 u32 dclr1; /* DRAM Configuration Low DCT1 reg */
344 u32 dchr0; /* DRAM Configuration High DCT0 reg */
345 u32 dchr1; /* DRAM Configuration High DCT1 reg */
346 u32 nbcap; /* North Bridge Capabilities */
347 u32 nbcfg; /* F10 North Bridge Configuration */
348 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
349 u32 dhar; /* DRAM Hoist reg */
350 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
351 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
354 struct chip_select csels[NUM_CONTROLLERS];
357 struct dram_range ranges[DRAM_RANGES];
359 u64 top_mem; /* top of memory below 4GB */
360 u64 top_mem2; /* top of memory above 4GB */
362 u32 dct_sel_lo; /* DRAM Controller Select Low */
363 u32 dct_sel_hi; /* DRAM Controller Select High */
364 u32 online_spare; /* On-Line spare Reg */
367 u8 ecc_sym_sz;
369 const char *ctl_name;
370 u16 f1_id, f2_id;
372 u8 max_mcs;
374 struct amd64_family_flags flags;
376 struct error_injection injection;
384 enum mem_type dram_type;
386 struct amd64_umc *umc; /* UMC registers */