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Lines Matching refs:tmp

188 	uint32_t tmp;  in gfxhub_v2_0_init_tlb_regs()  local
191 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_0_init_tlb_regs()
193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs()
194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v2_0_init_tlb_regs()
195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs()
197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs()
199 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs()
202 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_0_init_tlb_regs()
207 uint32_t tmp; in gfxhub_v2_0_init_cache_regs() local
214 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_0_init_cache_regs()
215 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v2_0_init_cache_regs()
216 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); in gfxhub_v2_0_init_cache_regs()
217 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v2_0_init_cache_regs()
220 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v2_0_init_cache_regs()
222 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); in gfxhub_v2_0_init_cache_regs()
223 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gfxhub_v2_0_init_cache_regs()
224 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); in gfxhub_v2_0_init_cache_regs()
225 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); in gfxhub_v2_0_init_cache_regs()
227 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_0_init_cache_regs()
228 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v2_0_init_cache_regs()
229 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v2_0_init_cache_regs()
230 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); in gfxhub_v2_0_init_cache_regs()
232 tmp = mmGCVM_L2_CNTL3_DEFAULT; in gfxhub_v2_0_init_cache_regs()
234 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v2_0_init_cache_regs()
235 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v2_0_init_cache_regs()
238 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v2_0_init_cache_regs()
239 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v2_0_init_cache_regs()
242 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); in gfxhub_v2_0_init_cache_regs()
244 tmp = mmGCVM_L2_CNTL4_DEFAULT; in gfxhub_v2_0_init_cache_regs()
245 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); in gfxhub_v2_0_init_cache_regs()
246 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); in gfxhub_v2_0_init_cache_regs()
247 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); in gfxhub_v2_0_init_cache_regs()
249 tmp = mmGCVM_L2_CNTL5_DEFAULT; in gfxhub_v2_0_init_cache_regs()
250 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); in gfxhub_v2_0_init_cache_regs()
251 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); in gfxhub_v2_0_init_cache_regs()
256 uint32_t tmp; in gfxhub_v2_0_enable_system_domain() local
258 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); in gfxhub_v2_0_enable_system_domain()
259 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v2_0_enable_system_domain()
260 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gfxhub_v2_0_enable_system_domain()
261 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, in gfxhub_v2_0_enable_system_domain()
263 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); in gfxhub_v2_0_enable_system_domain()
287 uint32_t tmp; in gfxhub_v2_0_setup_vmid_config() local
290 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); in gfxhub_v2_0_setup_vmid_config()
291 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v2_0_setup_vmid_config()
292 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v2_0_setup_vmid_config()
294 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_0_setup_vmid_config()
296 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_0_setup_vmid_config()
298 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_0_setup_vmid_config()
300 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_0_setup_vmid_config()
302 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_0_setup_vmid_config()
304 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_0_setup_vmid_config()
306 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_0_setup_vmid_config()
308 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_0_setup_vmid_config()
312 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_0_setup_vmid_config()
316 i * hub->ctx_distance, tmp); in gfxhub_v2_0_setup_vmid_config()
329 hub->vm_cntx_cntl = tmp; in gfxhub_v2_0_setup_vmid_config()
364 u32 tmp; in gfxhub_v2_0_gart_disable() local
373 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_0_gart_disable()
374 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v2_0_gart_disable()
375 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_gart_disable()
377 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_0_gart_disable()
395 u32 tmp; in gfxhub_v2_0_set_fault_enable_default() local
397 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_0_set_fault_enable_default()
398 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_0_set_fault_enable_default()
400 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_0_set_fault_enable_default()
402 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_0_set_fault_enable_default()
404 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_0_set_fault_enable_default()
406 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_0_set_fault_enable_default()
409 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_0_set_fault_enable_default()
411 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_0_set_fault_enable_default()
413 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_0_set_fault_enable_default()
415 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_0_set_fault_enable_default()
417 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_0_set_fault_enable_default()
419 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_0_set_fault_enable_default()
422 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_0_set_fault_enable_default()
424 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_0_set_fault_enable_default()
427 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v2_0_set_fault_enable_default()