Lines Matching refs:tmp
189 uint32_t tmp; in gfxhub_v2_1_init_tlb_regs() local
192 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_1_init_tlb_regs()
194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_1_init_tlb_regs()
195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v2_1_init_tlb_regs()
196 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_1_init_tlb_regs()
198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_1_init_tlb_regs()
200 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_1_init_tlb_regs()
203 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_1_init_tlb_regs()
208 uint32_t tmp; in gfxhub_v2_1_init_cache_regs() local
217 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_1_init_cache_regs()
218 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v2_1_init_cache_regs()
219 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); in gfxhub_v2_1_init_cache_regs()
220 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v2_1_init_cache_regs()
223 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v2_1_init_cache_regs()
225 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); in gfxhub_v2_1_init_cache_regs()
226 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gfxhub_v2_1_init_cache_regs()
227 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); in gfxhub_v2_1_init_cache_regs()
228 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); in gfxhub_v2_1_init_cache_regs()
230 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_1_init_cache_regs()
231 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v2_1_init_cache_regs()
232 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v2_1_init_cache_regs()
233 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); in gfxhub_v2_1_init_cache_regs()
235 tmp = mmGCVM_L2_CNTL3_DEFAULT; in gfxhub_v2_1_init_cache_regs()
237 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v2_1_init_cache_regs()
238 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v2_1_init_cache_regs()
241 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v2_1_init_cache_regs()
242 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v2_1_init_cache_regs()
245 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); in gfxhub_v2_1_init_cache_regs()
247 tmp = mmGCVM_L2_CNTL4_DEFAULT; in gfxhub_v2_1_init_cache_regs()
248 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); in gfxhub_v2_1_init_cache_regs()
249 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); in gfxhub_v2_1_init_cache_regs()
250 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); in gfxhub_v2_1_init_cache_regs()
252 tmp = mmGCVM_L2_CNTL5_DEFAULT; in gfxhub_v2_1_init_cache_regs()
253 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); in gfxhub_v2_1_init_cache_regs()
254 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); in gfxhub_v2_1_init_cache_regs()
259 uint32_t tmp; in gfxhub_v2_1_enable_system_domain() local
261 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); in gfxhub_v2_1_enable_system_domain()
262 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v2_1_enable_system_domain()
263 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gfxhub_v2_1_enable_system_domain()
264 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, in gfxhub_v2_1_enable_system_domain()
266 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); in gfxhub_v2_1_enable_system_domain()
296 uint32_t tmp; in gfxhub_v2_1_setup_vmid_config() local
299 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); in gfxhub_v2_1_setup_vmid_config()
300 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v2_1_setup_vmid_config()
301 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v2_1_setup_vmid_config()
303 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_1_setup_vmid_config()
305 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_1_setup_vmid_config()
307 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_1_setup_vmid_config()
309 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_1_setup_vmid_config()
311 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_1_setup_vmid_config()
313 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_1_setup_vmid_config()
315 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_1_setup_vmid_config()
317 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_1_setup_vmid_config()
321 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_1_setup_vmid_config()
325 i * hub->ctx_distance, tmp); in gfxhub_v2_1_setup_vmid_config()
338 hub->vm_cntx_cntl = tmp; in gfxhub_v2_1_setup_vmid_config()
385 u32 tmp; in gfxhub_v2_1_gart_disable() local
394 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_1_gart_disable()
395 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v2_1_gart_disable()
396 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_1_gart_disable()
398 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_1_gart_disable()
417 u32 tmp; in gfxhub_v2_1_set_fault_enable_default() local
425 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_1_set_fault_enable_default()
426 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_1_set_fault_enable_default()
428 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_1_set_fault_enable_default()
430 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_1_set_fault_enable_default()
432 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_1_set_fault_enable_default()
434 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_1_set_fault_enable_default()
437 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_1_set_fault_enable_default()
439 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_1_set_fault_enable_default()
441 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_1_set_fault_enable_default()
443 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_1_set_fault_enable_default()
445 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_1_set_fault_enable_default()
447 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_1_set_fault_enable_default()
450 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_1_set_fault_enable_default()
452 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v2_1_set_fault_enable_default()
455 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v2_1_set_fault_enable_default()
544 u32 tmp = 0, disabled_sa = 0; in gfxhub_v2_1_utcl2_harvest() local
570 tmp |= 0x3 << (i * 2); in gfxhub_v2_1_utcl2_harvest()
573 disabled_sa = tmp; in gfxhub_v2_1_utcl2_harvest()
658 uint32_t tmp; in gfxhub_v2_1_halt() local
675 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); in gfxhub_v2_1_halt()
676 while ((tmp & (GRBM_STATUS2__EA_BUSY_MASK | in gfxhub_v2_1_halt()
681 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); in gfxhub_v2_1_halt()