Lines Matching refs:tmp
192 uint32_t tmp; in gfxhub_v3_0_3_init_tlb_regs() local
195 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v3_0_3_init_tlb_regs()
197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v3_0_3_init_tlb_regs()
198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v3_0_3_init_tlb_regs()
199 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_3_init_tlb_regs()
201 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_3_init_tlb_regs()
203 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v3_0_3_init_tlb_regs()
204 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_3_init_tlb_regs()
207 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v3_0_3_init_tlb_regs()
212 uint32_t tmp; in gfxhub_v3_0_3_init_cache_regs() local
221 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); in gfxhub_v3_0_3_init_cache_regs()
222 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v3_0_3_init_cache_regs()
223 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); in gfxhub_v3_0_3_init_cache_regs()
224 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v3_0_3_init_cache_regs()
227 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v3_0_3_init_cache_regs()
229 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); in gfxhub_v3_0_3_init_cache_regs()
230 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gfxhub_v3_0_3_init_cache_regs()
231 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); in gfxhub_v3_0_3_init_cache_regs()
232 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); in gfxhub_v3_0_3_init_cache_regs()
234 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2); in gfxhub_v3_0_3_init_cache_regs()
235 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v3_0_3_init_cache_regs()
236 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v3_0_3_init_cache_regs()
237 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp); in gfxhub_v3_0_3_init_cache_regs()
239 tmp = regGCVM_L2_CNTL3_DEFAULT; in gfxhub_v3_0_3_init_cache_regs()
241 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v3_0_3_init_cache_regs()
242 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v3_0_3_init_cache_regs()
245 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v3_0_3_init_cache_regs()
246 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v3_0_3_init_cache_regs()
249 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v3_0_3_init_cache_regs()
251 tmp = regGCVM_L2_CNTL4_DEFAULT; in gfxhub_v3_0_3_init_cache_regs()
252 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); in gfxhub_v3_0_3_init_cache_regs()
253 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); in gfxhub_v3_0_3_init_cache_regs()
254 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp); in gfxhub_v3_0_3_init_cache_regs()
256 tmp = regGCVM_L2_CNTL5_DEFAULT; in gfxhub_v3_0_3_init_cache_regs()
257 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); in gfxhub_v3_0_3_init_cache_regs()
258 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp); in gfxhub_v3_0_3_init_cache_regs()
263 uint32_t tmp; in gfxhub_v3_0_3_enable_system_domain() local
265 tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL); in gfxhub_v3_0_3_enable_system_domain()
266 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v3_0_3_enable_system_domain()
267 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gfxhub_v3_0_3_enable_system_domain()
268 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, in gfxhub_v3_0_3_enable_system_domain()
270 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp); in gfxhub_v3_0_3_enable_system_domain()
300 uint32_t tmp; in gfxhub_v3_0_3_setup_vmid_config() local
303 tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i); in gfxhub_v3_0_3_setup_vmid_config()
304 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v3_0_3_setup_vmid_config()
305 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v3_0_3_setup_vmid_config()
307 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_3_setup_vmid_config()
309 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_3_setup_vmid_config()
311 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_3_setup_vmid_config()
313 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_3_setup_vmid_config()
315 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_3_setup_vmid_config()
317 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_3_setup_vmid_config()
319 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_3_setup_vmid_config()
321 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_3_setup_vmid_config()
325 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_3_setup_vmid_config()
329 i * hub->ctx_distance, tmp); in gfxhub_v3_0_3_setup_vmid_config()
342 hub->vm_cntx_cntl = tmp; in gfxhub_v3_0_3_setup_vmid_config()
377 u32 tmp; in gfxhub_v3_0_3_gart_disable() local
386 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v3_0_3_gart_disable()
387 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v3_0_3_gart_disable()
388 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v3_0_3_gart_disable()
390 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v3_0_3_gart_disable()
406 u32 tmp; in gfxhub_v3_0_3_set_fault_enable_default() local
414 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v3_0_3_set_fault_enable_default()
415 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_3_set_fault_enable_default()
417 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_3_set_fault_enable_default()
419 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_3_set_fault_enable_default()
421 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_3_set_fault_enable_default()
423 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_3_set_fault_enable_default()
426 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_3_set_fault_enable_default()
428 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_3_set_fault_enable_default()
430 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_3_set_fault_enable_default()
432 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_3_set_fault_enable_default()
434 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_3_set_fault_enable_default()
436 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_3_set_fault_enable_default()
439 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_3_set_fault_enable_default()
441 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v3_0_3_set_fault_enable_default()
444 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v3_0_3_set_fault_enable_default()