Lines Matching refs:tmp
109 u32 tmp; in gmc_v7_0_mc_resume() local
112 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_resume()
113 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v7_0_mc_resume()
114 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v7_0_mc_resume()
116 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v7_0_mc_resume()
117 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); in gmc_v7_0_mc_resume()
118 WREG32(mmBIF_FB_EN, tmp); in gmc_v7_0_mc_resume()
256 u32 tmp; in gmc_v7_0_mc_program() local
274 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v7_0_mc_program()
275 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v7_0_mc_program()
276 WREG32(mmVGA_HDP_CONTROL, tmp); in gmc_v7_0_mc_program()
279 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v7_0_mc_program()
280 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in gmc_v7_0_mc_program()
281 WREG32(mmVGA_RENDER_CONTROL, tmp); in gmc_v7_0_mc_program()
298 tmp = RREG32(mmHDP_MISC_CNTL); in gmc_v7_0_mc_program()
299 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); in gmc_v7_0_mc_program()
300 WREG32(mmHDP_MISC_CNTL, tmp); in gmc_v7_0_mc_program()
302 tmp = RREG32(mmHDP_HOST_PATH_CNTL); in gmc_v7_0_mc_program()
303 WREG32(mmHDP_HOST_PATH_CNTL, tmp); in gmc_v7_0_mc_program()
321 u32 tmp; in gmc_v7_0_mc_init() local
325 tmp = RREG32(mmMC_ARB_RAMCFG); in gmc_v7_0_mc_init()
326 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) in gmc_v7_0_mc_init()
331 tmp = RREG32(mmMC_SHARED_CHMAP); in gmc_v7_0_mc_init()
332 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v7_0_mc_init()
430 unsigned int tmp; in gmc_v7_0_flush_gpu_tlb_pasid() local
437 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); in gmc_v7_0_flush_gpu_tlb_pasid()
438 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && in gmc_v7_0_flush_gpu_tlb_pasid()
439 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) { in gmc_v7_0_flush_gpu_tlb_pasid()
519 u32 tmp; in gmc_v7_0_set_fault_enable_default() local
521 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_set_fault_enable_default()
522 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
524 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
526 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
528 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
530 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
532 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
534 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_set_fault_enable_default()
545 uint32_t tmp; in gmc_v7_0_set_prt() local
552 tmp = RREG32(mmVM_PRT_CNTL); in gmc_v7_0_set_prt()
553 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v7_0_set_prt()
555 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v7_0_set_prt()
557 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v7_0_set_prt()
559 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v7_0_set_prt()
561 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v7_0_set_prt()
563 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v7_0_set_prt()
565 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v7_0_set_prt()
567 WREG32(mmVM_PRT_CNTL, tmp); in gmc_v7_0_set_prt()
608 u32 tmp, field; in gmc_v7_0_gart_enable() local
619 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); in gmc_v7_0_gart_enable()
620 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gmc_v7_0_gart_enable()
621 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); in gmc_v7_0_gart_enable()
622 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gmc_v7_0_gart_enable()
623 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); in gmc_v7_0_gart_enable()
624 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); in gmc_v7_0_gart_enable()
625 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v7_0_gart_enable()
627 tmp = RREG32(mmVM_L2_CNTL); in gmc_v7_0_gart_enable()
628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
629 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gmc_v7_0_gart_enable()
630 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
631 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
632 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); in gmc_v7_0_gart_enable()
633 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gmc_v7_0_gart_enable()
634 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); in gmc_v7_0_gart_enable()
635 WREG32(mmVM_L2_CNTL, tmp); in gmc_v7_0_gart_enable()
636 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v7_0_gart_enable()
637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
638 WREG32(mmVM_L2_CNTL2, tmp); in gmc_v7_0_gart_enable()
641 tmp = RREG32(mmVM_L2_CNTL3); in gmc_v7_0_gart_enable()
642 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); in gmc_v7_0_gart_enable()
643 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v7_0_gart_enable()
644 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); in gmc_v7_0_gart_enable()
645 WREG32(mmVM_L2_CNTL3, tmp); in gmc_v7_0_gart_enable()
653 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v7_0_gart_enable()
654 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v7_0_gart_enable()
655 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gmc_v7_0_gart_enable()
656 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v7_0_gart_enable()
657 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v7_0_gart_enable()
683 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_gart_enable()
684 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gmc_v7_0_gart_enable()
685 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); in gmc_v7_0_gart_enable()
686 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, in gmc_v7_0_gart_enable()
688 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_gart_enable()
695 tmp = RREG32(mmCHUB_CONTROL); in gmc_v7_0_gart_enable()
696 tmp &= ~BYPASS_VM; in gmc_v7_0_gart_enable()
697 WREG32(mmCHUB_CONTROL, tmp); in gmc_v7_0_gart_enable()
733 u32 tmp; in gmc_v7_0_gart_disable() local
739 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); in gmc_v7_0_gart_disable()
740 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gmc_v7_0_gart_disable()
741 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); in gmc_v7_0_gart_disable()
742 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); in gmc_v7_0_gart_disable()
743 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v7_0_gart_disable()
745 tmp = RREG32(mmVM_L2_CNTL); in gmc_v7_0_gart_disable()
746 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v7_0_gart_disable()
747 WREG32(mmVM_L2_CNTL, tmp); in gmc_v7_0_gart_disable()
987 u32 tmp = RREG32(mmMC_SEQ_MISC0); in gmc_v7_0_sw_init() local
989 tmp &= MC_SEQ_MISC0__MT__MASK; in gmc_v7_0_sw_init()
990 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp); in gmc_v7_0_sw_init()
1052 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); in gmc_v7_0_sw_init() local
1054 tmp <<= 22; in gmc_v7_0_sw_init()
1055 adev->vm_manager.vram_base_offset = tmp; in gmc_v7_0_sw_init()
1146 u32 tmp = RREG32(mmSRBM_STATUS); in gmc_v7_0_is_idle() local
1148 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | in gmc_v7_0_is_idle()
1158 u32 tmp; in gmc_v7_0_wait_for_idle() local
1163 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | in gmc_v7_0_wait_for_idle()
1168 if (!tmp) in gmc_v7_0_wait_for_idle()
1180 u32 tmp = RREG32(mmSRBM_STATUS); in gmc_v7_0_soft_reset() local
1182 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) in gmc_v7_0_soft_reset()
1186 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | in gmc_v7_0_soft_reset()
1198 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v7_0_soft_reset()
1199 tmp |= srbm_soft_reset; in gmc_v7_0_soft_reset()
1200 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in gmc_v7_0_soft_reset()
1201 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v7_0_soft_reset()
1202 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v7_0_soft_reset()
1206 tmp &= ~srbm_soft_reset; in gmc_v7_0_soft_reset()
1207 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v7_0_soft_reset()
1208 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v7_0_soft_reset()
1225 u32 tmp; in gmc_v7_0_vm_fault_interrupt_state() local
1236 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1237 tmp &= ~bits; in gmc_v7_0_vm_fault_interrupt_state()
1238 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
1240 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1241 tmp &= ~bits; in gmc_v7_0_vm_fault_interrupt_state()
1242 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
1246 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1247 tmp |= bits; in gmc_v7_0_vm_fault_interrupt_state()
1248 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
1250 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1251 tmp |= bits; in gmc_v7_0_vm_fault_interrupt_state()
1252 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()