Lines Matching refs:ctx
96 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, in decon_set_bits() argument
99 val = (val & mask) | (readl(ctx->addr + reg) & ~mask); in decon_set_bits()
100 writel(val, ctx->addr + reg); in decon_set_bits()
105 struct decon_context *ctx = crtc->ctx; in decon_enable_vblank() local
114 writel(val, ctx->addr + DECON_VIDINTCON0); in decon_enable_vblank()
116 enable_irq(ctx->irq); in decon_enable_vblank()
117 if (!(ctx->out_type & I80_HW_TRG)) in decon_enable_vblank()
118 enable_irq(ctx->te_irq); in decon_enable_vblank()
125 struct decon_context *ctx = crtc->ctx; in decon_disable_vblank() local
127 if (!(ctx->out_type & I80_HW_TRG)) in decon_disable_vblank()
128 disable_irq_nosync(ctx->te_irq); in decon_disable_vblank()
129 disable_irq_nosync(ctx->irq); in decon_disable_vblank()
131 writel(0, ctx->addr + DECON_VIDINTCON0); in decon_disable_vblank()
135 static u32 decon_get_frame_count(struct decon_context *ctx, bool end) in decon_get_frame_count() argument
143 frm = readl(ctx->addr + DECON_CRFMID); in decon_get_frame_count()
145 status = readl(ctx->addr + DECON_VIDCON1); in decon_get_frame_count()
147 frm = readl(ctx->addr + DECON_CRFMID); in decon_get_frame_count()
158 if (!(ctx->crtc->i80_mode)) in decon_get_frame_count()
176 static void decon_setup_trigger(struct decon_context *ctx) in decon_setup_trigger() argument
178 if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG)) in decon_setup_trigger()
181 if (!(ctx->out_type & I80_HW_TRG)) { in decon_setup_trigger()
184 ctx->addr + DECON_TRIGCON); in decon_setup_trigger()
189 | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON); in decon_setup_trigger()
191 if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX, in decon_setup_trigger()
193 DRM_DEV_ERROR(ctx->dev, "Cannot update sysreg.\n"); in decon_setup_trigger()
198 struct decon_context *ctx = crtc->ctx; in decon_commit() local
203 if (ctx->out_type & IFTYPE_HDMI) { in decon_commit()
212 decon_setup_trigger(ctx); in decon_commit()
224 writel(val, ctx->addr + DECON_VIDOUTCON0); in decon_commit()
232 writel(val, ctx->addr + DECON_VIDTCON2); in decon_commit()
241 writel(val, ctx->addr + DECON_VIDTCON00); in decon_commit()
245 writel(val, ctx->addr + DECON_VIDTCON01); in decon_commit()
251 writel(val, ctx->addr + DECON_VIDTCON10); in decon_commit()
255 writel(val, ctx->addr + DECON_VIDTCON11); in decon_commit()
259 decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0); in decon_commit()
261 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); in decon_commit()
264 static void decon_win_set_bldeq(struct decon_context *ctx, unsigned int win, in decon_win_set_bldeq() argument
287 decon_set_bits(ctx, DECON_BLENDERQx(win), mask, val); in decon_win_set_bldeq()
290 static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win, in decon_win_set_bldmod() argument
307 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_BLEND_MODE_MASK, val); in decon_win_set_bldmod()
313 decon_set_bits(ctx, DECON_VIDOSDxC(win), in decon_win_set_bldmod()
315 decon_set_bits(ctx, DECON_BLENDCON, BLEND_NEW, BLEND_NEW); in decon_win_set_bldmod()
319 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, in decon_win_set_pixfmt() argument
322 struct exynos_drm_plane *plane = &ctx->planes[win]; in decon_win_set_pixfmt()
334 val = readl(ctx->addr + DECON_WINCONx(win)); in decon_win_set_pixfmt()
361 DRM_DEV_DEBUG_KMS(ctx->dev, "cpp = %u\n", fb->format->cpp[0]); in decon_win_set_pixfmt()
375 decon_set_bits(ctx, DECON_WINCONx(win), ~WINCONx_BLEND_MODE_MASK, val); in decon_win_set_pixfmt()
378 decon_win_set_bldmod(ctx, win, alpha, pixel_alpha); in decon_win_set_pixfmt()
379 decon_win_set_bldeq(ctx, win, alpha, pixel_alpha); in decon_win_set_pixfmt()
383 static void decon_shadow_protect(struct decon_context *ctx, bool protect) in decon_shadow_protect() argument
385 decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK, in decon_shadow_protect()
391 struct decon_context *ctx = crtc->ctx; in decon_atomic_begin() local
393 decon_shadow_protect(ctx, true); in decon_atomic_begin()
405 struct decon_context *ctx = crtc->ctx; in decon_update_plane() local
416 writel(val, ctx->addr + DECON_VIDOSDxA(win)); in decon_update_plane()
420 writel(val, ctx->addr + DECON_VIDOSDxB(win)); in decon_update_plane()
423 writel(val, ctx->addr + DECON_VIDOSDxA(win)); in decon_update_plane()
427 writel(val, ctx->addr + DECON_VIDOSDxB(win)); in decon_update_plane()
432 writel(val, ctx->addr + DECON_VIDOSDxC(win)); in decon_update_plane()
436 writel(val, ctx->addr + DECON_VIDOSDxD(win)); in decon_update_plane()
438 writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win)); in decon_update_plane()
441 writel(val, ctx->addr + DECON_VIDW0xADD1B0(win)); in decon_update_plane()
443 if (!(ctx->out_type & IFTYPE_HDMI)) in decon_update_plane()
449 writel(val, ctx->addr + DECON_VIDW0xADD2(win)); in decon_update_plane()
451 decon_win_set_pixfmt(ctx, win, fb); in decon_update_plane()
454 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0); in decon_update_plane()
460 struct decon_context *ctx = crtc->ctx; in decon_disable_plane() local
463 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); in decon_disable_plane()
468 struct decon_context *ctx = crtc->ctx; in decon_atomic_flush() local
471 spin_lock_irqsave(&ctx->vblank_lock, flags); in decon_atomic_flush()
473 decon_shadow_protect(ctx, false); in decon_atomic_flush()
475 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); in decon_atomic_flush()
477 ctx->frame_id = decon_get_frame_count(ctx, true); in decon_atomic_flush()
481 spin_unlock_irqrestore(&ctx->vblank_lock, flags); in decon_atomic_flush()
484 static void decon_swreset(struct decon_context *ctx) in decon_swreset() argument
490 writel(0, ctx->addr + DECON_VIDCON0); in decon_swreset()
491 readl_poll_timeout(ctx->addr + DECON_VIDCON0, val, in decon_swreset()
494 writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0); in decon_swreset()
495 ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val, in decon_swreset()
500 spin_lock_irqsave(&ctx->vblank_lock, flags); in decon_swreset()
501 ctx->frame_id = 0; in decon_swreset()
502 spin_unlock_irqrestore(&ctx->vblank_lock, flags); in decon_swreset()
504 if (!(ctx->out_type & IFTYPE_HDMI)) in decon_swreset()
507 writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0); in decon_swreset()
508 decon_set_bits(ctx, DECON_CMU, in decon_swreset()
510 writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1); in decon_swreset()
512 ctx->addr + DECON_CRCCTRL); in decon_swreset()
517 struct decon_context *ctx = crtc->ctx; in decon_atomic_enable() local
520 ret = pm_runtime_resume_and_get(ctx->dev); in decon_atomic_enable()
522 DRM_DEV_ERROR(ctx->dev, "failed to enable DECON device.\n"); in decon_atomic_enable()
528 decon_swreset(ctx); in decon_atomic_enable()
530 decon_commit(ctx->crtc); in decon_atomic_enable()
535 struct decon_context *ctx = crtc->ctx; in decon_atomic_disable() local
538 if (!(ctx->out_type & I80_HW_TRG)) in decon_atomic_disable()
539 synchronize_irq(ctx->te_irq); in decon_atomic_disable()
540 synchronize_irq(ctx->irq); in decon_atomic_disable()
547 for (i = ctx->first_win; i < WINDOWS_NR; i++) in decon_atomic_disable()
548 decon_disable_plane(crtc, &ctx->planes[i]); in decon_atomic_disable()
550 decon_swreset(ctx); in decon_atomic_disable()
554 pm_runtime_put_sync(ctx->dev); in decon_atomic_disable()
559 struct decon_context *ctx = dev_id; in decon_te_irq_handler() local
561 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0); in decon_te_irq_handler()
568 struct decon_context *ctx = crtc->ctx; in decon_clear_channels() local
572 ret = clk_prepare_enable(ctx->clks[i]); in decon_clear_channels()
577 decon_shadow_protect(ctx, true); in decon_clear_channels()
579 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); in decon_clear_channels()
580 decon_shadow_protect(ctx, false); in decon_clear_channels()
582 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); in decon_clear_channels()
589 clk_disable_unprepare(ctx->clks[i]); in decon_clear_channels()
595 struct decon_context *ctx = crtc->ctx; in decon_mode_valid() local
597 ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync; in decon_mode_valid()
599 if (ctx->irq) in decon_mode_valid()
602 dev_info(ctx->dev, "Sink requires %s mode, but appropriate interrupt is not provided.\n", in decon_mode_valid()
622 struct decon_context *ctx = dev_get_drvdata(dev); in decon_bind() local
629 ctx->drm_dev = drm_dev; in decon_bind()
631 for (win = ctx->first_win; win < WINDOWS_NR; win++) { in decon_bind()
632 ctx->configs[win].pixel_formats = decon_formats; in decon_bind()
633 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats); in decon_bind()
634 ctx->configs[win].zpos = win - ctx->first_win; in decon_bind()
635 ctx->configs[win].type = decon_win_types[win]; in decon_bind()
636 ctx->configs[win].capabilities = capabilities[win]; in decon_bind()
638 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win, in decon_bind()
639 &ctx->configs[win]); in decon_bind()
644 exynos_plane = &ctx->planes[PRIMARY_WIN]; in decon_bind()
645 out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI in decon_bind()
647 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, in decon_bind()
648 out_type, &decon_crtc_ops, ctx); in decon_bind()
649 if (IS_ERR(ctx->crtc)) in decon_bind()
650 return PTR_ERR(ctx->crtc); in decon_bind()
652 decon_clear_channels(ctx->crtc); in decon_bind()
654 return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv); in decon_bind()
659 struct decon_context *ctx = dev_get_drvdata(dev); in decon_unbind() local
661 decon_atomic_disable(ctx->crtc); in decon_unbind()
664 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv); in decon_unbind()
672 static void decon_handle_vblank(struct decon_context *ctx) in decon_handle_vblank() argument
676 spin_lock(&ctx->vblank_lock); in decon_handle_vblank()
678 frm = decon_get_frame_count(ctx, true); in decon_handle_vblank()
680 if (frm != ctx->frame_id) { in decon_handle_vblank()
682 if ((s32)(frm - ctx->frame_id) > 0) in decon_handle_vblank()
683 drm_crtc_handle_vblank(&ctx->crtc->base); in decon_handle_vblank()
684 ctx->frame_id = frm; in decon_handle_vblank()
687 spin_unlock(&ctx->vblank_lock); in decon_handle_vblank()
692 struct decon_context *ctx = dev_id; in decon_irq_handler() local
695 val = readl(ctx->addr + DECON_VIDINTCON1); in decon_irq_handler()
699 writel(val, ctx->addr + DECON_VIDINTCON1); in decon_irq_handler()
700 if (ctx->out_type & IFTYPE_HDMI) { in decon_irq_handler()
701 val = readl(ctx->addr + DECON_VIDOUTCON0); in decon_irq_handler()
707 decon_handle_vblank(ctx); in decon_irq_handler()
715 struct decon_context *ctx = dev_get_drvdata(dev); in exynos5433_decon_suspend() local
719 clk_disable_unprepare(ctx->clks[i]); in exynos5433_decon_suspend()
726 struct decon_context *ctx = dev_get_drvdata(dev); in exynos5433_decon_resume() local
730 ret = clk_prepare_enable(ctx->clks[i]); in exynos5433_decon_resume()
739 clk_disable_unprepare(ctx->clks[i]); in exynos5433_decon_resume()
761 static int decon_conf_irq(struct decon_context *ctx, const char *name, in decon_conf_irq() argument
764 struct platform_device *pdev = to_platform_device(ctx->dev); in decon_conf_irq()
775 dev_err(ctx->dev, "IRQ %s get failed, %d\n", name, irq); in decon_conf_irq()
779 ret = devm_request_irq(ctx->dev, irq, handler, in decon_conf_irq()
780 flags | IRQF_NO_AUTOEN, "drm_decon", ctx); in decon_conf_irq()
782 dev_err(ctx->dev, "IRQ %s request failed\n", name); in decon_conf_irq()
792 struct decon_context *ctx; in exynos5433_decon_probe() local
796 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); in exynos5433_decon_probe()
797 if (!ctx) in exynos5433_decon_probe()
800 ctx->dev = dev; in exynos5433_decon_probe()
801 ctx->out_type = (unsigned long)of_device_get_match_data(dev); in exynos5433_decon_probe()
802 spin_lock_init(&ctx->vblank_lock); in exynos5433_decon_probe()
804 if (ctx->out_type & IFTYPE_HDMI) in exynos5433_decon_probe()
805 ctx->first_win = 1; in exynos5433_decon_probe()
810 clk = devm_clk_get(ctx->dev, decon_clks_name[i]); in exynos5433_decon_probe()
814 ctx->clks[i] = clk; in exynos5433_decon_probe()
817 ctx->addr = devm_platform_ioremap_resource(pdev, 0); in exynos5433_decon_probe()
818 if (IS_ERR(ctx->addr)) in exynos5433_decon_probe()
819 return PTR_ERR(ctx->addr); in exynos5433_decon_probe()
821 ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0); in exynos5433_decon_probe()
824 ctx->irq_vsync = ret; in exynos5433_decon_probe()
826 ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0); in exynos5433_decon_probe()
829 ctx->irq_lcd_sys = ret; in exynos5433_decon_probe()
831 ret = decon_conf_irq(ctx, "te", decon_te_irq_handler, in exynos5433_decon_probe()
836 ctx->te_irq = ret; in exynos5433_decon_probe()
837 ctx->out_type &= ~I80_HW_TRG; in exynos5433_decon_probe()
840 if (ctx->out_type & I80_HW_TRG) { in exynos5433_decon_probe()
841 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, in exynos5433_decon_probe()
843 if (IS_ERR(ctx->sysreg)) { in exynos5433_decon_probe()
845 return PTR_ERR(ctx->sysreg); in exynos5433_decon_probe()
849 platform_set_drvdata(pdev, ctx); in exynos5433_decon_probe()