185 	trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),  in intel_vgpu_reg_imr_handler()
186 		       (vgpu_vreg(vgpu, reg) ^ imr));  in intel_vgpu_reg_imr_handler()
188 	vgpu_vreg(vgpu, reg) = imr;  in intel_vgpu_reg_imr_handler()
214 	u32 virtual_ier = vgpu_vreg(vgpu, reg);  in intel_vgpu_reg_master_irq_handler()
226 	vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;  in intel_vgpu_reg_master_irq_handler()
227 	vgpu_vreg(vgpu, reg) |= ier;  in intel_vgpu_reg_master_irq_handler()
256 	trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),  in intel_vgpu_reg_ier_handler()
257 		       (vgpu_vreg(vgpu, reg) ^ ier));  in intel_vgpu_reg_ier_handler()
259 	vgpu_vreg(vgpu, reg) = ier;  in intel_vgpu_reg_ier_handler()
294 	trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),  in intel_vgpu_reg_iir_handler()
295 		       (vgpu_vreg(vgpu, reg) ^ iir));  in intel_vgpu_reg_iir_handler()
300 	vgpu_vreg(vgpu, reg) &= ~iir;  in intel_vgpu_reg_iir_handler()
334 	u32 val = vgpu_vreg(vgpu,  in update_upstream_irq()
336 		& vgpu_vreg(vgpu,  in update_upstream_irq()
366 		vgpu_vreg(vgpu, isr) &= ~clear_bits;  in update_upstream_irq()
367 		vgpu_vreg(vgpu, isr) |= set_bits;  in update_upstream_irq()
374 		vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));  in update_upstream_irq()
456 	if (!test_bit(bit, (void *)&vgpu_vreg(vgpu,  in propagate_event()
459 		set_bit(bit, (void *)&vgpu_vreg(vgpu,  in propagate_event()
511 	if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &  in gen8_check_pending_irq()
523 		if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base))  in gen8_check_pending_irq()
524 				& vgpu_vreg(vgpu, regbase_to_ier(reg_base))))  in gen8_check_pending_irq()
528 	if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))  in gen8_check_pending_irq()