204 	u32 *cs;  in restore_context_mmio_for_inhibit()  local
218 	cs = intel_ring_begin(req, count * 2 + 2);  in restore_context_mmio_for_inhibit()
219 	if (IS_ERR(cs))  in restore_context_mmio_for_inhibit()
220 		return PTR_ERR(cs);  in restore_context_mmio_for_inhibit()
222 	*cs++ = MI_LOAD_REGISTER_IMM(count);  in restore_context_mmio_for_inhibit()
228 		*cs++ = i915_mmio_reg_offset(mmio->reg);  in restore_context_mmio_for_inhibit()
229 		*cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16);  in restore_context_mmio_for_inhibit()
231 			      *(cs-2), *(cs-1), vgpu->id, ring_id);  in restore_context_mmio_for_inhibit()
234 	*cs++ = MI_NOOP;  in restore_context_mmio_for_inhibit()
235 	intel_ring_advance(req, cs);  in restore_context_mmio_for_inhibit()
249 	u32 *cs;  in restore_render_mocs_control_for_inhibit()  local
251 	cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE + 2);  in restore_render_mocs_control_for_inhibit()
252 	if (IS_ERR(cs))  in restore_render_mocs_control_for_inhibit()
253 		return PTR_ERR(cs);  in restore_render_mocs_control_for_inhibit()
255 	*cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE);  in restore_render_mocs_control_for_inhibit()
258 		*cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index));  in restore_render_mocs_control_for_inhibit()
259 		*cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index));  in restore_render_mocs_control_for_inhibit()
261 			      *(cs-2), *(cs-1), vgpu->id, req->engine->id);  in restore_render_mocs_control_for_inhibit()
265 	*cs++ = MI_NOOP;  in restore_render_mocs_control_for_inhibit()
266 	intel_ring_advance(req, cs);  in restore_render_mocs_control_for_inhibit()
276 	u32 *cs;  in restore_render_mocs_l3cc_for_inhibit()  local
278 	cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE / 2 + 2);  in restore_render_mocs_l3cc_for_inhibit()
279 	if (IS_ERR(cs))  in restore_render_mocs_l3cc_for_inhibit()
280 		return PTR_ERR(cs);  in restore_render_mocs_l3cc_for_inhibit()
282 	*cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2);  in restore_render_mocs_l3cc_for_inhibit()
285 		*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index));  in restore_render_mocs_l3cc_for_inhibit()
286 		*cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index));  in restore_render_mocs_l3cc_for_inhibit()
288 			      *(cs-2), *(cs-1), vgpu->id, req->engine->id);  in restore_render_mocs_l3cc_for_inhibit()
292 	*cs++ = MI_NOOP;  in restore_render_mocs_l3cc_for_inhibit()
293 	intel_ring_advance(req, cs);  in restore_render_mocs_l3cc_for_inhibit()
307 	u32 *cs;  in intel_vgpu_restore_inhibit_context()  local
309 	cs = intel_ring_begin(req, 2);  in intel_vgpu_restore_inhibit_context()
310 	if (IS_ERR(cs))  in intel_vgpu_restore_inhibit_context()
311 		return PTR_ERR(cs);  in intel_vgpu_restore_inhibit_context()
313 	*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;  in intel_vgpu_restore_inhibit_context()
314 	*cs++ = MI_NOOP;  in intel_vgpu_restore_inhibit_context()
315 	intel_ring_advance(req, cs);  in intel_vgpu_restore_inhibit_context()
334 	cs = intel_ring_begin(req, 2);  in intel_vgpu_restore_inhibit_context()
335 	if (IS_ERR(cs))  in intel_vgpu_restore_inhibit_context()
336 		return PTR_ERR(cs);  in intel_vgpu_restore_inhibit_context()
338 	*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;  in intel_vgpu_restore_inhibit_context()
339 	*cs++ = MI_NOOP;  in intel_vgpu_restore_inhibit_context()
340 	intel_ring_advance(req, cs);  in intel_vgpu_restore_inhibit_context()