101 	struct dpu_hw_blk_reg_map *c = &ctx->hw;  in dpu_hw_intf_setup_timing_engine()  local
117 	intf_cfg = DPU_REG_READ(c, INTF_CONFIG);  in dpu_hw_intf_setup_timing_engine()
207 	DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl);  in dpu_hw_intf_setup_timing_engine()
208 	DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period);  in dpu_hw_intf_setup_timing_engine()
209 	DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0,  in dpu_hw_intf_setup_timing_engine()
211 	DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl);  in dpu_hw_intf_setup_timing_engine()
212 	DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start);  in dpu_hw_intf_setup_timing_engine()
213 	DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end);  in dpu_hw_intf_setup_timing_engine()
214 	DPU_REG_WRITE(c, INTF_ACTIVE_HCTL,  active_hctl);  in dpu_hw_intf_setup_timing_engine()
215 	DPU_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start);  in dpu_hw_intf_setup_timing_engine()
216 	DPU_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end);  in dpu_hw_intf_setup_timing_engine()
217 	DPU_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr);  in dpu_hw_intf_setup_timing_engine()
218 	DPU_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr);  in dpu_hw_intf_setup_timing_engine()
219 	DPU_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew);  in dpu_hw_intf_setup_timing_engine()
220 	DPU_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl);  in dpu_hw_intf_setup_timing_engine()
221 	DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3);  in dpu_hw_intf_setup_timing_engine()
222 	DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg);  in dpu_hw_intf_setup_timing_engine()
223 	DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);  in dpu_hw_intf_setup_timing_engine()
233 		DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2);  in dpu_hw_intf_setup_timing_engine()
234 		DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl);  in dpu_hw_intf_setup_timing_engine()
235 		DPU_REG_WRITE(c, INTF_ACTIVE_DATA_HCTL, active_data_hctl);  in dpu_hw_intf_setup_timing_engine()
243 	struct dpu_hw_blk_reg_map *c = &intf->hw;  in dpu_hw_intf_enable_timing_engine()  local
245 	DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0);  in dpu_hw_intf_enable_timing_engine()
252 	struct dpu_hw_blk_reg_map *c = &intf->hw;  in dpu_hw_intf_setup_prg_fetch()  local
260 	fetch_enable = DPU_REG_READ(c, INTF_CONFIG);  in dpu_hw_intf_setup_prg_fetch()
263 		DPU_REG_WRITE(c, INTF_PROG_FETCH_START,  in dpu_hw_intf_setup_prg_fetch()
269 	DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable);  in dpu_hw_intf_setup_prg_fetch()
276 	struct dpu_hw_blk_reg_map *c = &intf->hw;  in dpu_hw_intf_bind_pingpong_blk()  local
279 	mux_cfg = DPU_REG_READ(c, INTF_MUX);  in dpu_hw_intf_bind_pingpong_blk()
287 	DPU_REG_WRITE(c, INTF_MUX, mux_cfg);  in dpu_hw_intf_bind_pingpong_blk()
294 	struct dpu_hw_blk_reg_map *c = &intf->hw;  in dpu_hw_intf_get_status()  local
298 		s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0);  in dpu_hw_intf_get_status()
300 		s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);  in dpu_hw_intf_get_status()
302 	s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31));  in dpu_hw_intf_get_status()
304 		s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT);  in dpu_hw_intf_get_status()
305 		s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT);  in dpu_hw_intf_get_status()
314 	struct dpu_hw_blk_reg_map *c;  in dpu_hw_intf_get_line_count()  local
319 	c = &intf->hw;  in dpu_hw_intf_get_line_count()
321 	return DPU_REG_READ(c, INTF_LINE_COUNT);  in dpu_hw_intf_get_line_count()
337 	struct dpu_hw_blk_reg_map *c;  in dpu_hw_intf_enable_te()  local
343 	c = &intf->hw;  in dpu_hw_intf_enable_te()
351 	DPU_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg);  in dpu_hw_intf_enable_te()
352 	DPU_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);  in dpu_hw_intf_enable_te()
353 	DPU_REG_WRITE(c, INTF_TEAR_VSYNC_INIT_VAL, te->vsync_init_val);  in dpu_hw_intf_enable_te()
354 	DPU_REG_WRITE(c, INTF_TEAR_RD_PTR_IRQ, te->rd_ptr_irq);  in dpu_hw_intf_enable_te()
355 	DPU_REG_WRITE(c, INTF_TEAR_START_POS, te->start_pos);  in dpu_hw_intf_enable_te()
356 	DPU_REG_WRITE(c, INTF_TEAR_SYNC_THRESH,  in dpu_hw_intf_enable_te()
359 	DPU_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT,  in dpu_hw_intf_enable_te()
362 	DPU_REG_WRITE(c, INTF_TEAR_TEAR_CHECK_EN, 1);  in dpu_hw_intf_enable_te()
370 	struct dpu_hw_blk_reg_map *c;  in dpu_hw_intf_setup_autorefresh_config()  local
373 	c = &intf->hw;  in dpu_hw_intf_setup_autorefresh_config()
374 	refresh_cfg = DPU_REG_READ(c, INTF_TEAR_AUTOREFRESH_CONFIG);  in dpu_hw_intf_setup_autorefresh_config()
380 	DPU_REG_WRITE(c, INTF_TEAR_AUTOREFRESH_CONFIG, refresh_cfg);  in dpu_hw_intf_setup_autorefresh_config()
402 	struct dpu_hw_blk_reg_map *c;  in dpu_hw_intf_disable_te()  local
407 	c = &intf->hw;  in dpu_hw_intf_disable_te()
408 	DPU_REG_WRITE(c, INTF_TEAR_TEAR_CHECK_EN, 0);  in dpu_hw_intf_disable_te()
415 	struct dpu_hw_blk_reg_map *c = &intf->hw;  in dpu_hw_intf_connect_external_te()  local
422 	c = &intf->hw;  in dpu_hw_intf_connect_external_te()
423 	cfg = DPU_REG_READ(c, INTF_TEAR_SYNC_CONFIG_VSYNC);  in dpu_hw_intf_connect_external_te()
429 	DPU_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg);  in dpu_hw_intf_connect_external_te()
438 	struct dpu_hw_blk_reg_map *c = &intf->hw;  in dpu_hw_intf_get_vsync_info()  local
444 	c = &intf->hw;  in dpu_hw_intf_get_vsync_info()
446 	val = DPU_REG_READ(c, INTF_TEAR_VSYNC_INIT_VAL);  in dpu_hw_intf_get_vsync_info()
449 	val = DPU_REG_READ(c, INTF_TEAR_INT_COUNT_VAL);  in dpu_hw_intf_get_vsync_info()
453 	val = DPU_REG_READ(c, INTF_TEAR_LINE_COUNT);  in dpu_hw_intf_get_vsync_info()
456 	val = DPU_REG_READ(c, INTF_FRAME_COUNT);  in dpu_hw_intf_get_vsync_info()
465 	struct dpu_hw_blk_reg_map *c;  in dpu_hw_intf_vsync_sel()  local
470 	c = &intf->hw;  in dpu_hw_intf_vsync_sel()
472 	DPU_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (vsync_source & 0xf));  in dpu_hw_intf_vsync_sel()
558 	struct dpu_hw_intf *c;  in dpu_hw_intf_init()  local
565 	c = kzalloc(sizeof(*c), GFP_KERNEL);  in dpu_hw_intf_init()
566 	if (!c)  in dpu_hw_intf_init()
569 	c->hw.blk_addr = addr + cfg->base;  in dpu_hw_intf_init()
570 	c->hw.log_mask = DPU_DBG_MASK_INTF;  in dpu_hw_intf_init()
575 	c->idx = cfg->id;  in dpu_hw_intf_init()
576 	c->cap = cfg;  in dpu_hw_intf_init()
577 	_setup_intf_ops(&c->ops, c->cap->features, mdss_rev);  in dpu_hw_intf_init()
579 	return c;  in dpu_hw_intf_init()