48 	struct dpu_hw_blk_reg_map *c;  in dpu_hw_pp_setup_dither()  local
51 	c = &pp->hw;  in dpu_hw_pp_setup_dither()
54 		DPU_REG_WRITE(c, base + PP_DITHER_EN, 0);  in dpu_hw_pp_setup_dither()
64 	DPU_REG_WRITE(c, base + PP_DITHER_BITDEPTH, data);  in dpu_hw_pp_setup_dither()
71 		DPU_REG_WRITE(c, base + PP_DITHER_MATRIX + i, data);  in dpu_hw_pp_setup_dither()
73 	DPU_REG_WRITE(c, base + PP_DITHER_EN, 1);  in dpu_hw_pp_setup_dither()
79 	struct dpu_hw_blk_reg_map *c;  in dpu_hw_pp_enable_te()  local
84 	c = &pp->hw;  in dpu_hw_pp_enable_te()
92 	DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);  in dpu_hw_pp_enable_te()
93 	DPU_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);  in dpu_hw_pp_enable_te()
94 	DPU_REG_WRITE(c, PP_VSYNC_INIT_VAL, te->vsync_init_val);  in dpu_hw_pp_enable_te()
95 	DPU_REG_WRITE(c, PP_RD_PTR_IRQ, te->rd_ptr_irq);  in dpu_hw_pp_enable_te()
96 	DPU_REG_WRITE(c, PP_START_POS, te->start_pos);  in dpu_hw_pp_enable_te()
97 	DPU_REG_WRITE(c, PP_SYNC_THRESH,  in dpu_hw_pp_enable_te()
100 	DPU_REG_WRITE(c, PP_SYNC_WRCOUNT,  in dpu_hw_pp_enable_te()
103 	DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, 1);  in dpu_hw_pp_enable_te()
133 	struct dpu_hw_blk_reg_map *c;  in dpu_hw_pp_disable_te()  local
137 	c = &pp->hw;  in dpu_hw_pp_disable_te()
139 	DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, 0);  in dpu_hw_pp_disable_te()
146 	struct dpu_hw_blk_reg_map *c = &pp->hw;  in dpu_hw_pp_connect_external_te()  local
153 	c = &pp->hw;  in dpu_hw_pp_connect_external_te()
154 	cfg = DPU_REG_READ(c, PP_SYNC_CONFIG_VSYNC);  in dpu_hw_pp_connect_external_te()
160 	DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);  in dpu_hw_pp_connect_external_te()
169 	struct dpu_hw_blk_reg_map *c;  in dpu_hw_pp_get_vsync_info()  local
174 	c = &pp->hw;  in dpu_hw_pp_get_vsync_info()
176 	val = DPU_REG_READ(c, PP_VSYNC_INIT_VAL);  in dpu_hw_pp_get_vsync_info()
179 	val = DPU_REG_READ(c, PP_INT_COUNT_VAL);  in dpu_hw_pp_get_vsync_info()
183 	val = DPU_REG_READ(c, PP_LINE_COUNT);  in dpu_hw_pp_get_vsync_info()
191 	struct dpu_hw_blk_reg_map *c = &pp->hw;  in dpu_hw_pp_get_line_count()  local
197 	c = &pp->hw;  in dpu_hw_pp_get_line_count()
199 	init = DPU_REG_READ(c, PP_VSYNC_INIT_VAL) & 0xFFFF;  in dpu_hw_pp_get_line_count()
200 	height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0xFFFF;  in dpu_hw_pp_get_line_count()
205 	line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0xFFFF;  in dpu_hw_pp_get_line_count()
260 	struct dpu_hw_blk_reg_map *c = &pp->hw;  in dpu_hw_pp_dsc_enable()  local
262 	DPU_REG_WRITE(c, PP_DSC_MODE, 1);  in dpu_hw_pp_dsc_enable()
268 	struct dpu_hw_blk_reg_map *c = &pp->hw;  in dpu_hw_pp_dsc_disable()  local
270 	DPU_REG_WRITE(c, PP_DSC_MODE, 0);  in dpu_hw_pp_dsc_disable()
284 static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,  in _setup_pingpong_ops()  argument
288 		c->ops.enable_tearcheck = dpu_hw_pp_enable_te;  in _setup_pingpong_ops()
289 		c->ops.disable_tearcheck = dpu_hw_pp_disable_te;  in _setup_pingpong_ops()
290 		c->ops.connect_external_te = dpu_hw_pp_connect_external_te;  in _setup_pingpong_ops()
291 		c->ops.get_line_count = dpu_hw_pp_get_line_count;  in _setup_pingpong_ops()
292 		c->ops.disable_autorefresh = dpu_hw_pp_disable_autorefresh;  in _setup_pingpong_ops()
296 		c->ops.setup_dsc = dpu_hw_pp_setup_dsc;  in _setup_pingpong_ops()
297 		c->ops.enable_dsc = dpu_hw_pp_dsc_enable;  in _setup_pingpong_ops()
298 		c->ops.disable_dsc = dpu_hw_pp_dsc_disable;  in _setup_pingpong_ops()
302 		c->ops.setup_dither = dpu_hw_pp_setup_dither;  in _setup_pingpong_ops()
308 	struct dpu_hw_pingpong *c;  in dpu_hw_pingpong_init()  local
310 	c = kzalloc(sizeof(*c), GFP_KERNEL);  in dpu_hw_pingpong_init()
311 	if (!c)  in dpu_hw_pingpong_init()
314 	c->hw.blk_addr = addr + cfg->base;  in dpu_hw_pingpong_init()
315 	c->hw.log_mask = DPU_DBG_MASK_PINGPONG;  in dpu_hw_pingpong_init()
317 	c->idx = cfg->id;  in dpu_hw_pingpong_init()
318 	c->caps = cfg;  in dpu_hw_pingpong_init()
319 	_setup_pingpong_ops(c, c->caps->features);  in dpu_hw_pingpong_init()
321 	return c;  in dpu_hw_pingpong_init()