128 static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk,  in pll_get_integloop_gain()  argument
131 	int digclk_divsel = bclk >= HDMI_DIG_FREQ_BIT_CLK_THRESHOLD ? 1 : 2;  in pll_get_integloop_gain()
166 static int pll_get_post_div(struct hdmi_8996_post_divider *pd, u64 bclk)  in pll_get_post_div()  argument
185 			vco = bclk >> half_rate_mode;  in pll_get_post_div()
222 	u64 bclk;  in pll_calculate()  local
237 	bclk = ((u64)pix_clk) * 10;  in pll_calculate()
239 	if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD)  in pll_calculate()
244 	ret = pll_get_post_div(&pd, bclk);  in pll_calculate()
262 	integloop_gain = pll_get_integloop_gain(frac_start, bclk,  in pll_calculate()
285 	if (bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD)  in pll_calculate()
306 	cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0;  in pll_calculate()
320 	if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) {  in pll_calculate()
341 	} else if (bclk > HDMI_MID_FREQ_BIT_CLK_THRESHOLD) {  in pll_calculate()