Lines Matching refs:nv_crtc
65 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_set_digital_vibrance() local
67 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_digital_vibrance()
69 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; in nv_crtc_set_digital_vibrance()
70 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { in nv_crtc_set_digital_vibrance()
72 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; in nv_crtc_set_digital_vibrance()
80 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_set_image_sharpening() local
82 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_image_sharpening()
84 nv_crtc->sharpness = level; in nv_crtc_set_image_sharpening()
88 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); in nv_crtc_set_image_sharpening()
123 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_calc_state_ext() local
125 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; in nv_crtc_calc_state_ext()
129 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, in nv_crtc_calc_state_ext()
162 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; in nv_crtc_calc_state_ext()
171 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); in nv_crtc_calc_state_ext()
177 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_dpms() local
184 nv_crtc->index); in nv_crtc_dpms()
186 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */ in nv_crtc_dpms()
189 nv_crtc->last_dpms = mode; in nv_crtc_dpms()
192 NVSetOwner(dev, nv_crtc->index); in nv_crtc_dpms()
195 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index, in nv_crtc_dpms()
224 NVVgaSeqReset(dev, nv_crtc->index, true); in nv_crtc_dpms()
226 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); in nv_crtc_dpms()
227 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); in nv_crtc_dpms()
228 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80); in nv_crtc_dpms()
230 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); in nv_crtc_dpms()
231 NVVgaSeqReset(dev, nv_crtc->index, false); in nv_crtc_dpms()
233 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); in nv_crtc_dpms()
240 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_mode_set_vga() local
241 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_vga()
465 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_mode_set_regs() local
466 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_regs()
467 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_regs()
498 if (nv_crtc->index == 0) in nv_crtc_mode_set_regs()
504 if (pPriv->overlayCRTC == nv_crtc->index) in nv_crtc_mode_set_regs()
534 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); in nv_crtc_mode_set_regs()
541 if (nv_crtc->index == 0) in nv_crtc_mode_set_regs()
547 if (!nv_crtc->index) in nv_crtc_mode_set_regs()
600 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); in nv_crtc_mode_set_regs()
615 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_swap_fbs() local
620 if (disp->image[nv_crtc->index]) in nv_crtc_swap_fbs()
621 nouveau_bo_unpin(disp->image[nv_crtc->index]); in nv_crtc_swap_fbs()
622 nouveau_bo_ref(nvbo, &disp->image[nv_crtc->index]); in nv_crtc_swap_fbs()
642 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_mode_set() local
646 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index); in nv_crtc_mode_set()
654 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1); in nv_crtc_mode_set()
667 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_save() local
670 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; in nv_crtc_save()
672 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index]; in nv_crtc_save()
675 NVSetOwner(crtc->dev, nv_crtc->index); in nv_crtc_save()
677 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); in nv_crtc_save()
688 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_restore() local
690 int head = nv_crtc->index; in nv_crtc_restore()
699 nv_crtc->last_dpms = NV_DPMS_CLEARED; in nv_crtc_restore()
706 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_prepare() local
710 NVSetOwner(dev, nv_crtc->index); in nv_crtc_prepare()
715 NVBlankScreen(dev, nv_crtc->index, true); in nv_crtc_prepare()
718 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); in nv_crtc_prepare()
720 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); in nv_crtc_prepare()
721 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); in nv_crtc_prepare()
729 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_commit() local
731 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); in nv_crtc_commit()
737 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR); in nv_crtc_commit()
739 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); in nv_crtc_commit()
750 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_destroy() local
752 if (!nv_crtc) in nv_crtc_destroy()
757 if (disp->image[nv_crtc->index]) in nv_crtc_destroy()
758 nouveau_bo_unpin(disp->image[nv_crtc->index]); in nv_crtc_destroy()
759 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); in nv_crtc_destroy()
761 nouveau_bo_unmap(nv_crtc->cursor.nvbo); in nv_crtc_destroy()
762 nouveau_bo_unpin(nv_crtc->cursor.nvbo); in nv_crtc_destroy()
763 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); in nv_crtc_destroy()
764 nvif_event_dtor(&nv_crtc->vblank); in nv_crtc_destroy()
765 nvif_head_dtor(&nv_crtc->head); in nv_crtc_destroy()
766 kfree(nv_crtc); in nv_crtc_destroy()
772 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_gamma_load() local
773 struct drm_device *dev = nv_crtc->base.dev; in nv_crtc_gamma_load()
778 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; in nv_crtc_gamma_load()
789 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); in nv_crtc_gamma_load()
796 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_disable() local
797 if (disp->image[nv_crtc->index]) in nv_crtc_disable()
798 nouveau_bo_unpin(disp->image[nv_crtc->index]); in nv_crtc_disable()
799 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); in nv_crtc_disable()
807 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_gamma_set() local
814 if (!nv_crtc->base.primary->fb) { in nv_crtc_gamma_set()
815 nv_crtc->lut.depth = 0; in nv_crtc_gamma_set()
829 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv04_crtc_do_mode_set_base() local
832 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_crtc_do_mode_set_base()
837 NV_DEBUG(drm, "index %d\n", nv_crtc->index); in nv04_crtc_do_mode_set_base()
855 nv_crtc->fb.offset = nvbo->offset; in nv04_crtc_do_mode_set_base()
857 if (nv_crtc->lut.depth != drm_fb->format->depth) { in nv04_crtc_do_mode_set_base()
858 nv_crtc->lut.depth = drm_fb->format->depth; in nv04_crtc_do_mode_set_base()
869 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, in nv04_crtc_do_mode_set_base()
882 regp->fb_start = nv_crtc->fb.offset & ~3; in nv04_crtc_do_mode_set_base()
884 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); in nv04_crtc_do_mode_set_base()
987 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv04_crtc_cursor_set() local
993 nv_crtc->cursor.hide(nv_crtc, true); in nv04_crtc_cursor_set()
1010 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); in nv04_crtc_cursor_set()
1012 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); in nv04_crtc_cursor_set()
1015 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->offset; in nv04_crtc_cursor_set()
1016 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); in nv04_crtc_cursor_set()
1017 nv_crtc->cursor.show(nv_crtc, true); in nv04_crtc_cursor_set()
1026 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv04_crtc_cursor_move() local
1028 nv_crtc->cursor.set_pos(nv_crtc, x, y); in nv04_crtc_cursor_move()
1278 struct nouveau_crtc *nv_crtc = container_of(event, struct nouveau_crtc, vblank); in nv04_crtc_vblank_handler() local
1280 drm_crtc_handle_vblank(&nv_crtc->base); in nv04_crtc_vblank_handler()
1288 struct nouveau_crtc *nv_crtc; in nv04_crtc_create() local
1292 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); in nv04_crtc_create()
1293 if (!nv_crtc) in nv04_crtc_create()
1296 nv_crtc->lut.depth = 0; in nv04_crtc_create()
1298 nv_crtc->index = crtc_num; in nv04_crtc_create()
1299 nv_crtc->last_dpms = NV_DPMS_CLEARED; in nv04_crtc_create()
1301 nv_crtc->save = nv_crtc_save; in nv04_crtc_create()
1302 nv_crtc->restore = nv_crtc_restore; in nv04_crtc_create()
1311 kfree(nv_crtc); in nv04_crtc_create()
1315 drm_crtc_init_with_planes(dev, &nv_crtc->base, primary, NULL, in nv04_crtc_create()
1317 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); in nv04_crtc_create()
1318 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); in nv04_crtc_create()
1322 &nv_crtc->cursor.nvbo); in nv04_crtc_create()
1324 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, in nv04_crtc_create()
1327 ret = nouveau_bo_map(nv_crtc->cursor.nvbo); in nv04_crtc_create()
1329 nouveau_bo_unpin(nv_crtc->cursor.nvbo); in nv04_crtc_create()
1332 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); in nv04_crtc_create()
1335 nv04_cursor_init(nv_crtc); in nv04_crtc_create()
1337 ret = nvif_head_ctor(&disp->disp, nv_crtc->base.name, nv_crtc->index, &nv_crtc->head); in nv04_crtc_create()
1341 return nvif_head_vblank_event_ctor(&nv_crtc->head, "kmsVbl", nv04_crtc_vblank_handler, in nv04_crtc_create()
1342 false, &nv_crtc->vblank); in nv04_crtc_create()