Lines Matching refs:clk
65 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll) in gk20a_pllg_read_mnp() argument
67 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_read_mnp()
77 gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll) in gk20a_pllg_write_mnp() argument
79 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_write_mnp()
89 gk20a_pllg_calc_rate(struct gk20a_clk *clk, struct gk20a_pll *pll) in gk20a_pllg_calc_rate() argument
94 rate = clk->parent_rate * pll->n; in gk20a_pllg_calc_rate()
95 divider = pll->m * clk->pl_to_div(pll->pl); in gk20a_pllg_calc_rate()
101 gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate, in gk20a_pllg_calc_mnp() argument
104 struct nvkm_subdev *subdev = &clk->base.subdev; in gk20a_pllg_calc_mnp()
114 ref_clk_f = clk->parent_rate / KHZ; in gk20a_pllg_calc_mnp()
117 max_vco_f = max(clk->params->max_vco, target_vco_f); in gk20a_pllg_calc_mnp()
118 min_vco_f = clk->params->min_vco; in gk20a_pllg_calc_mnp()
119 best_m = clk->params->max_m; in gk20a_pllg_calc_mnp()
120 best_n = clk->params->min_n; in gk20a_pllg_calc_mnp()
121 best_pl = clk->params->min_pl; in gk20a_pllg_calc_mnp()
125 high_pl = min(high_pl, clk->params->max_pl); in gk20a_pllg_calc_mnp()
126 high_pl = max(high_pl, clk->params->min_pl); in gk20a_pllg_calc_mnp()
127 high_pl = clk->div_to_pl(high_pl); in gk20a_pllg_calc_mnp()
131 low_pl = min(low_pl, clk->params->max_pl); in gk20a_pllg_calc_mnp()
132 low_pl = max(low_pl, clk->params->min_pl); in gk20a_pllg_calc_mnp()
133 low_pl = clk->div_to_pl(low_pl); in gk20a_pllg_calc_mnp()
136 clk->pl_to_div(low_pl), high_pl, clk->pl_to_div(high_pl)); in gk20a_pllg_calc_mnp()
142 target_vco_f = target_clk_f * clk->pl_to_div(pl); in gk20a_pllg_calc_mnp()
144 for (m = clk->params->min_m; m <= clk->params->max_m; m++) { in gk20a_pllg_calc_mnp()
147 if (u_f < clk->params->min_u) in gk20a_pllg_calc_mnp()
149 if (u_f > clk->params->max_u) in gk20a_pllg_calc_mnp()
155 if (n > clk->params->max_n) in gk20a_pllg_calc_mnp()
161 if (n < clk->params->min_n) in gk20a_pllg_calc_mnp()
163 if (n > clk->params->max_n) in gk20a_pllg_calc_mnp()
171 lwv = (vco_f + (clk->pl_to_div(pl) / 2)) in gk20a_pllg_calc_mnp()
172 / clk->pl_to_div(pl); in gk20a_pllg_calc_mnp()
201 target_freq = gk20a_pllg_calc_rate(clk, pll); in gk20a_pllg_calc_mnp()
206 clk->pl_to_div(pll->pl)); in gk20a_pllg_calc_mnp()
211 gk20a_pllg_slide(struct gk20a_clk *clk, u32 n) in gk20a_pllg_slide() argument
213 struct nvkm_subdev *subdev = &clk->base.subdev; in gk20a_pllg_slide()
219 gk20a_pllg_read_mnp(clk, &pll); in gk20a_pllg_slide()
232 gk20a_pllg_write_mnp(clk, &pll); in gk20a_pllg_slide()
256 gk20a_pllg_enable(struct gk20a_clk *clk) in gk20a_pllg_enable() argument
258 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_enable()
284 gk20a_pllg_disable(struct gk20a_clk *clk) in gk20a_pllg_disable() argument
286 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_disable()
296 gk20a_pllg_program_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll) in gk20a_pllg_program_mnp() argument
298 struct nvkm_subdev *subdev = &clk->base.subdev; in gk20a_pllg_program_mnp()
303 gk20a_pllg_read_mnp(clk, &cur_pll); in gk20a_pllg_program_mnp()
314 gk20a_pllg_disable(clk); in gk20a_pllg_program_mnp()
316 gk20a_pllg_write_mnp(clk, pll); in gk20a_pllg_program_mnp()
318 ret = gk20a_pllg_enable(clk); in gk20a_pllg_program_mnp()
335 gk20a_pllg_program_mnp_slide(struct gk20a_clk *clk, const struct gk20a_pll *pll) in gk20a_pllg_program_mnp_slide() argument
340 if (gk20a_pllg_is_enabled(clk)) { in gk20a_pllg_program_mnp_slide()
341 gk20a_pllg_read_mnp(clk, &cur_pll); in gk20a_pllg_program_mnp_slide()
345 return gk20a_pllg_slide(clk, pll->n); in gk20a_pllg_program_mnp_slide()
348 cur_pll.n = gk20a_pllg_n_lo(clk, &cur_pll); in gk20a_pllg_program_mnp_slide()
349 ret = gk20a_pllg_slide(clk, cur_pll.n); in gk20a_pllg_program_mnp_slide()
356 cur_pll.n = gk20a_pllg_n_lo(clk, &cur_pll); in gk20a_pllg_program_mnp_slide()
357 ret = gk20a_pllg_program_mnp(clk, &cur_pll); in gk20a_pllg_program_mnp_slide()
362 return gk20a_pllg_slide(clk, pll->n); in gk20a_pllg_program_mnp_slide()
462 struct gk20a_clk *clk = gk20a_clk(base); in gk20a_clk_read() local
463 struct nvkm_subdev *subdev = &clk->base.subdev; in gk20a_clk_read()
471 gk20a_pllg_read_mnp(clk, &pll); in gk20a_clk_read()
472 return gk20a_pllg_calc_rate(clk, &pll) / GK20A_CLK_GPC_MDIV; in gk20a_clk_read()
482 struct gk20a_clk *clk = gk20a_clk(base); in gk20a_clk_calc() local
484 return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] * in gk20a_clk_calc()
485 GK20A_CLK_GPC_MDIV, &clk->pll); in gk20a_clk_calc()
491 struct gk20a_clk *clk = gk20a_clk(base); in gk20a_clk_prog() local
494 ret = gk20a_pllg_program_mnp_slide(clk, &clk->pll); in gk20a_clk_prog()
496 ret = gk20a_pllg_program_mnp(clk, &clk->pll); in gk20a_clk_prog()
507 gk20a_clk_setup_slide(struct gk20a_clk *clk) in gk20a_clk_setup_slide() argument
509 struct nvkm_subdev *subdev = &clk->base.subdev; in gk20a_clk_setup_slide()
513 switch (clk->parent_rate) { in gk20a_clk_setup_slide()
530 clk->parent_rate / KHZ); in gk20a_clk_setup_slide()
546 struct gk20a_clk *clk = gk20a_clk(base); in gk20a_clk_fini() local
549 if (gk20a_pllg_is_enabled(clk)) { in gk20a_clk_fini()
553 gk20a_pllg_read_mnp(clk, &pll); in gk20a_clk_fini()
554 n_lo = gk20a_pllg_n_lo(clk, &pll); in gk20a_clk_fini()
555 gk20a_pllg_slide(clk, n_lo); in gk20a_clk_fini()
558 gk20a_pllg_disable(clk); in gk20a_clk_fini()
567 struct gk20a_clk *clk = gk20a_clk(base); in gk20a_clk_init() local
568 struct nvkm_subdev *subdev = &clk->base.subdev; in gk20a_clk_init()
580 ret = gk20a_clk_setup_slide(clk); in gk20a_clk_init()
586 ret = base->func->prog(&clk->base); in gk20a_clk_init()
615 struct gk20a_clk *clk) in gk20a_clk_ctor() argument
627 clk->params = params; in gk20a_clk_ctor()
628 clk->parent_rate = clk_get_rate(tdev->clk); in gk20a_clk_ctor()
630 ret = nvkm_clk_ctor(func, device, type, inst, true, &clk->base); in gk20a_clk_ctor()
634 nvkm_debug(&clk->base.subdev, "parent clock rate: %d Khz\n", in gk20a_clk_ctor()
635 clk->parent_rate / KHZ); in gk20a_clk_ctor()
644 struct gk20a_clk *clk; in gk20a_clk_new() local
647 clk = kzalloc(sizeof(*clk), GFP_KERNEL); in gk20a_clk_new()
648 if (!clk) in gk20a_clk_new()
650 *pclk = &clk->base; in gk20a_clk_new()
652 ret = gk20a_clk_ctor(device, type, inst, &gk20a_clk, &gk20a_pllg_params, clk); in gk20a_clk_new()
654 clk->pl_to_div = pl_to_div; in gk20a_clk_new()
655 clk->div_to_pl = div_to_pl; in gk20a_clk_new()