225 	nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,  in gk20a_pllg_slide()
236 	nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,  in gk20a_pllg_slide()
247 	nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,  in gk20a_pllg_slide()
261 	nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE);  in gk20a_pllg_enable()
277 	nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT),  in gk20a_pllg_enable()
289 	nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0);  in gk20a_pllg_disable()
291 	nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0);  in gk20a_pllg_disable()
306 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,  in gk20a_pllg_program_mnp()
309 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,  in gk20a_pllg_program_mnp()
324 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,  in gk20a_pllg_program_mnp()
327 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,  in gk20a_pllg_program_mnp()
534 	nvkm_mask(device, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT,  in gk20a_clk_setup_slide()
536 	nvkm_mask(device, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT,  in gk20a_clk_setup_slide()
561 	nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_IDDQ, 1);  in gk20a_clk_fini()
573 	nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_IDDQ, 0);  in gk20a_clk_init()
577 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK,  in gk20a_clk_init()