Lines Matching refs:tmp
200 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); in radeon_get_clock_info() local
203 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; in radeon_get_clock_info()
205 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; in radeon_get_clock_info()
393 uint32_t tmp; in radeon_legacy_set_engine_clock() local
400 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_engine_clock()
401 tmp &= ~RADEON_DONT_USE_XTALIN; in radeon_legacy_set_engine_clock()
402 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
404 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()
405 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_set_engine_clock()
406 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
410 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
411 tmp |= RADEON_SPLL_SLEEP; in radeon_legacy_set_engine_clock()
412 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
416 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
417 tmp |= RADEON_SPLL_RESET; in radeon_legacy_set_engine_clock()
418 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
422 tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_set_engine_clock()
423 tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT); in radeon_legacy_set_engine_clock()
424 tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT; in radeon_legacy_set_engine_clock()
425 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp); in radeon_legacy_set_engine_clock()
428 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
429 tmp &= ~RADEON_SPLL_PVG_MASK; in radeon_legacy_set_engine_clock()
431 tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT); in radeon_legacy_set_engine_clock()
433 tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT); in radeon_legacy_set_engine_clock()
434 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
436 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
437 tmp &= ~RADEON_SPLL_SLEEP; in radeon_legacy_set_engine_clock()
438 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
442 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()
443 tmp &= ~RADEON_SPLL_RESET; in radeon_legacy_set_engine_clock()
444 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
448 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()
449 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_set_engine_clock()
453 tmp |= 1; in radeon_legacy_set_engine_clock()
456 tmp |= 2; in radeon_legacy_set_engine_clock()
459 tmp |= 3; in radeon_legacy_set_engine_clock()
462 tmp |= 4; in radeon_legacy_set_engine_clock()
465 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
469 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_engine_clock()
470 tmp |= RADEON_DONT_USE_XTALIN; in radeon_legacy_set_engine_clock()
471 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
478 uint32_t tmp; in radeon_legacy_set_clock_gating() local
482 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
486 tmp &= in radeon_legacy_set_clock_gating()
490 tmp &= in radeon_legacy_set_clock_gating()
496 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
500 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
501 tmp &= in radeon_legacy_set_clock_gating()
515 tmp |= RADEON_DYN_STOP_LAT_MASK; in radeon_legacy_set_clock_gating()
516 tmp |= in radeon_legacy_set_clock_gating()
519 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
521 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
522 tmp &= ~RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
523 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; in radeon_legacy_set_clock_gating()
524 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
526 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
527 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
529 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
531 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
532 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
545 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
547 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
548 tmp &= ~(R300_SCLK_FORCE_TCL | in radeon_legacy_set_clock_gating()
551 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT | in radeon_legacy_set_clock_gating()
554 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
556 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
557 tmp &= in radeon_legacy_set_clock_gating()
571 tmp |= RADEON_DYN_STOP_LAT_MASK; in radeon_legacy_set_clock_gating()
572 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
574 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
575 tmp &= ~RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
576 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; in radeon_legacy_set_clock_gating()
577 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
579 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
580 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
582 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
584 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
585 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
598 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
600 tmp = RREG32_PLL(RADEON_MCLK_MISC); in radeon_legacy_set_clock_gating()
601 tmp |= (RADEON_MC_MCLK_DYN_ENABLE | in radeon_legacy_set_clock_gating()
603 WREG32_PLL(RADEON_MCLK_MISC, tmp); in radeon_legacy_set_clock_gating()
605 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
606 tmp |= (RADEON_FORCEON_MCLKA | in radeon_legacy_set_clock_gating()
609 tmp &= ~(RADEON_FORCEON_YCLKA | in radeon_legacy_set_clock_gating()
617 if ((tmp & R300_DISABLE_MC_MCLKA) && in radeon_legacy_set_clock_gating()
618 (tmp & R300_DISABLE_MC_MCLKB)) { in radeon_legacy_set_clock_gating()
620 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
624 tmp &= in radeon_legacy_set_clock_gating()
627 tmp &= in radeon_legacy_set_clock_gating()
630 tmp &= ~(R300_DISABLE_MC_MCLKA | in radeon_legacy_set_clock_gating()
635 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
637 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
638 tmp &= ~(R300_SCLK_FORCE_VAP); in radeon_legacy_set_clock_gating()
639 tmp |= RADEON_SCLK_FORCE_CP; in radeon_legacy_set_clock_gating()
640 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
643 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
644 tmp &= ~(R300_SCLK_FORCE_TCL | in radeon_legacy_set_clock_gating()
647 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
650 tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); in radeon_legacy_set_clock_gating()
652 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK | in radeon_legacy_set_clock_gating()
656 tmp |= (RADEON_ENGIN_DYNCLK_MODE | in radeon_legacy_set_clock_gating()
658 WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp); in radeon_legacy_set_clock_gating()
661 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_clock_gating()
662 tmp |= RADEON_SCLK_DYN_START_CNTL; in radeon_legacy_set_clock_gating()
663 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_clock_gating()
669 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
671 tmp &= ~RADEON_SCLK_FORCEON_MASK; in radeon_legacy_set_clock_gating()
683 tmp |= RADEON_SCLK_FORCE_CP; in radeon_legacy_set_clock_gating()
684 tmp |= RADEON_SCLK_FORCE_VIP; in radeon_legacy_set_clock_gating()
687 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
692 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
693 tmp &= ~RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
701 tmp |= RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
703 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
713 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); in radeon_legacy_set_clock_gating()
714 tmp |= RADEON_TCL_BYPASS_DISABLE; in radeon_legacy_set_clock_gating()
715 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); in radeon_legacy_set_clock_gating()
720 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
721 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
729 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
732 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
733 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
736 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
742 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
743 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP | in radeon_legacy_set_clock_gating()
750 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
753 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
754 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | in radeon_legacy_set_clock_gating()
762 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
764 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
765 tmp |= RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
766 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
768 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
769 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
772 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
774 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
775 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
789 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
792 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
793 tmp |= (R300_SCLK_FORCE_TCL | in radeon_legacy_set_clock_gating()
795 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
797 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
798 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | in radeon_legacy_set_clock_gating()
806 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
808 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
809 tmp |= RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
810 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
812 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
813 tmp |= (RADEON_FORCEON_MCLKA | in radeon_legacy_set_clock_gating()
817 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
819 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
820 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
823 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
825 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
826 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
840 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
842 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()
843 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2); in radeon_legacy_set_clock_gating()
844 tmp |= RADEON_SCLK_FORCE_SE; in radeon_legacy_set_clock_gating()
847 tmp |= (RADEON_SCLK_FORCE_RB | in radeon_legacy_set_clock_gating()
860 tmp |= (RADEON_SCLK_FORCE_HDP | in radeon_legacy_set_clock_gating()
867 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
873 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
874 tmp |= (R300_SCLK_FORCE_TCL | in radeon_legacy_set_clock_gating()
877 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
882 tmp = RREG32_PLL(RADEON_MCLK_CNTL); in radeon_legacy_set_clock_gating()
883 tmp &= ~(RADEON_FORCEON_MCLKA | in radeon_legacy_set_clock_gating()
885 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
892 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); in radeon_legacy_set_clock_gating()
893 tmp |= RADEON_SCLK_MORE_FORCEON; in radeon_legacy_set_clock_gating()
894 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
898 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_set_clock_gating()
899 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
907 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
910 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()
911 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | in radeon_legacy_set_clock_gating()
913 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()