926 	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);  in rv770_pcie_gart_enable()
927 	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);  in rv770_pcie_gart_enable()
938 		 (unsigned)(rdev->mc.gtt_size >> 20),  in rv770_pcie_gart_enable()
1032 		if (rdev->mc.vram_start < rdev->mc.gtt_start) {  in rv770_mc_program()
1035 				rdev->mc.vram_start >> 12);  in rv770_mc_program()
1037 				rdev->mc.gtt_end >> 12);  in rv770_mc_program()
1041 				rdev->mc.gtt_start >> 12);  in rv770_mc_program()
1043 				rdev->mc.vram_end >> 12);  in rv770_mc_program()
1047 			rdev->mc.vram_start >> 12);  in rv770_mc_program()
1049 			rdev->mc.vram_end >> 12);  in rv770_mc_program()
1052 	tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;  in rv770_mc_program()
1053 	tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);  in rv770_mc_program()
1055 	WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));  in rv770_mc_program()
1059 		WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);  in rv770_mc_program()
1060 		WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);  in rv770_mc_program()
1061 		WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);  in rv770_mc_program()
1083 		radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);  in r700_cp_stop()
1603 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)  in r700_vram_gtt_location()  argument
1607 	if (mc->mc_vram_size > 0xE0000000) {  in r700_vram_gtt_location()
1610 		mc->real_vram_size = 0xE0000000;  in r700_vram_gtt_location()
1611 		mc->mc_vram_size = 0xE0000000;  in r700_vram_gtt_location()
1614 		size_bf = mc->gtt_start;  in r700_vram_gtt_location()
1615 		size_af = mc->mc_mask - mc->gtt_end;  in r700_vram_gtt_location()
1617 			if (mc->mc_vram_size > size_bf) {  in r700_vram_gtt_location()
1619 				mc->real_vram_size = size_bf;  in r700_vram_gtt_location()
1620 				mc->mc_vram_size = size_bf;  in r700_vram_gtt_location()
1622 			mc->vram_start = mc->gtt_start - mc->mc_vram_size;  in r700_vram_gtt_location()
1624 			if (mc->mc_vram_size > size_af) {  in r700_vram_gtt_location()
1626 				mc->real_vram_size = size_af;  in r700_vram_gtt_location()
1627 				mc->mc_vram_size = size_af;  in r700_vram_gtt_location()
1629 			mc->vram_start = mc->gtt_end + 1;  in r700_vram_gtt_location()
1631 		mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;  in r700_vram_gtt_location()
1633 				mc->mc_vram_size >> 20, mc->vram_start,  in r700_vram_gtt_location()
1634 				mc->vram_end, mc->real_vram_size >> 20);  in r700_vram_gtt_location()
1636 		radeon_vram_location(rdev, &rdev->mc, 0);  in r700_vram_gtt_location()
1637 		rdev->mc.gtt_base_align = 0;  in r700_vram_gtt_location()
1638 		radeon_gtt_location(rdev, mc);  in r700_vram_gtt_location()
1648 	rdev->mc.vram_is_ddr = true;  in rv770_mc_init()
1673 	rdev->mc.vram_width = numchan * chansize;  in rv770_mc_init()
1675 	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);  in rv770_mc_init()
1676 	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);  in rv770_mc_init()
1678 	rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);  in rv770_mc_init()
1679 	rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);  in rv770_mc_init()
1680 	rdev->mc.visible_vram_size = rdev->mc.aper_size;  in rv770_mc_init()
1681 	r700_vram_gtt_location(rdev, &rdev->mc);  in rv770_mc_init()